Solid-state imaging device and electronic apparatus using the same
A solid-state imaging device includes a semiconductor substrate, a first pixel with a green color filter, a second pixel with a blue color filter and a third pixel with a red color filter. The first pixel includes a first area for generating an electric signal by photoelectric conversion, disposed in a first trench that is formed on a surface of the semiconductor substrate, and a first transistor area that outputs the electric signal obtained from the first area. The second pixel includes a second area formed in a flat shape on the surface of the semiconductor substrate, and a second transistor area that outputs the electric signal obtained from the second area. The third pixel includes a third area formed in a flat shape on the surface of the semiconductor substrate, and a third transistor area that outputs the electric signal obtained from the third area.
1. A solid-state imaging device comprising:
a semiconductor substrate;
a first pixel formed on the semiconductor substrate, the first pixel having a first color filter that exhibits higher transmissivity to a first visible light wavelength range of a green color than to other visible light wavelength ranges;
a second pixel formed on the semiconductor substrate, the second pixel having a second color filter that exhibits higher transmissivity to a second visible light wavelength range of a blue color than to other visible light wavelength ranges; and
a third pixel formed on the semiconductor substrate, the third pixel having a third color filter that exhibits higher transmissivity to a third visible light wavelength range of a red color than to other visible light wavelength ranges;
wherein the first pixel includes:
a first area disposed in a first trench that is formed on a surface of the semiconductor substrate, the first area configured to generate an electric signal by photoelectric conversion, and
a first transistor area that outputs the electric signal obtained from the first area as an output signal;
the second pixel includes:
a second area disposed in a second trench that is formed on a surface of the semiconductor substrate, the second area configured to generate an electric signal by photoelectric conversion, and
a second transistor area that outputs the electric signal obtained from the second area as an output signal; and
the third pixel includes:
a third area formed in a flat shape on the surface of the semiconductor substrate, the third area configured to generate an electric signal by photoelectric conversion, and
a third transistor area that outputs the electric signal obtained from the third area as an output signal.
2. The device according to claim 1 ,
wherein the first pixel further includes a first flat area formed in a flat shape on the semiconductor substrate, the first flat area configured to generate an electric signal by photoelectric conversion;
the first flat area is disposed in proximity to the first area so that the first flat area and the first area are integrally formed in the same layer; and
the first transistor area outputs the electric signal obtained in the first area and in the first flat are as the output signal.
3. The device according to claim 1 ,
wherein the second pixel further includes a second flat area formed in a flat shape on the semiconductor substrate, the second flat area configured to generate an electric signal by photoelectric conversion;
the second flat area is disposed in proximity to the second area so that the second flat area and the second area are integrally formed in the same layer; and
the second transistor area outputs the electric signal obtained in the second area and in the second flat area as the output signal.
4. The device according to claim 2 ,
wherein the first flat area has a peak value of a dopant concentration higher than the first area;
the first transistor area includes a transfer transistor disposed adjacently to the first flat area; and
the dopant concentration of the first flat area is determined to provide an electric potential that is lower than a channel potential achieved at the time of activation of the transfer transistor.
5. The device according to claim 3 ,
wherein the second flat area has a peak value of a dopant concentration higher than the second area;
the second transistor area includes a transfer transistor disposed adjacently to the second flat area; and
the dopant concentration of the second flat area is determined such that an electric potential of the second flat area is lower than a channel potential achieved at the time of activation of the transfer transistor.
6. The device according to claim 4 ,
wherein the first area and the first flat area include a multilayer structure having a first dopant diffusion layer of first conductivity type and a second dopant diffusion layer of second conductivity type provided underneath the first dopant diffusion layer.
7. The device according to claim 5 ,
wherein the second area and the second flat area include a multilayer structure having a third dopant diffusion layer of first conductivity type and a fourth dopant diffusion layer of second conductivity type provided underneath the third dopant diffusion layer.
8. The device according to claim 1 ,
wherein the first trench and the second trench has cross sections in a V-shape.
9. The device according to claim 1 ,
wherein the first trench and the second trench has cross sections having a stepped shape.
10. The device according to claim 1 ,
wherein the first pixel, the second pixel and the third pixel are arranged in a matrix pattern.
11. The device according to claim 1 , further comprising a fourth pixel formed on the semiconductor substrate, the fourth pixel having a transparent color filter.