IP Library › Granted Patent US 7,714,667
Granted Patent B2
US 7,714,667 · App. 11/934,426 · Granted May 11, 2010

Programmable linear trimming method and system for phase locked loop circuit calibration

Assignee: Agere Systems Inc.
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Quick Facts
Patent No.
US 7,714,667
App. No.
11/934,426
Granted
May 11, 2010
Kind
B2
Abstract

The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

Claims (32)

1. An apparatus for calibrating a phase locked loop (PLL) circuit, comprising:

a detector for detecting a frequency difference between a first frequency associated with a reference signal and a second frequency associated with a controlled oscillator contained in said PLL circuit and outputting said frequency difference;

a programmable control circuit operably connected to said detector, the programmable control circuit programmed to:

receive a set of values corresponding to an operating range of frequencies for the controlled oscillator;

receive said frequency difference;

assign a value to a variable within said set of operating values based on said frequency difference; and

supply control signals to said controlled oscillator based upon said variable; and

a state machine including said programmable control circuit, and the set of values includes a first value corresponding to an initial value of output from said state machine and a second value corresponding to an end value of output from said state machine.

2. The apparatus of claim 1 , further comprising a voltage controller for supplying said controlled oscillator with a reference voltage.

3. The apparatus of claim 2 , wherein said control circuit uses said voltage controller to control said second frequency associated with said controlled oscillator.

4. The apparatus of claim 3 , wherein said reference voltage is variably adjusted by said control circuit to adjust said second frequency associated with said controlled oscillator.

5. The apparatus of claim 4 , wherein said control circuit variably adjusts said reference voltage until said frequency difference is within a predetermined acceptable range.

6. The apparatus of claim 1 , further comprising a current controller for supplying said controlled oscillator with a reference current.

7. The apparatus of claim 6 , wherein said control circuit uses said currently controller to control said second frequency associated with said controlled oscillator.

8. The apparatus of claim 7 , wherein said reference currently is variably adjusted by said control circuit to adjust said second frequency associated with said controlled oscillator.

9. The apparatus of claim 8 , wherein said control circuit variably adjusts said reference currently until said frequency difference is within a predetermined acceptable range.

10. A method for calibrating a phase locked loop (PLL) circuit including a controlled oscillator and that receives a reference signal, the method comprising the steps of:

receiving a set of values corresponding to an operating range of frequencies for the controlled oscillator;

receiving said reference signal and a signal from said controlled oscillator and determining a frequency difference between said signals;

assigning a value to a variable within said set of operating values based on said frequency difference;

outputting an updated set of one or more control signals to said controlled oscillator based upon said variable; and

ceasing to output an updated set of one or more control signals to said controlled oscillator when said frequency difference is within a predetermined acceptable range, wherein said set of values includes a first value corresponding to an initial value of output from a state machine and a second value corresponding to an end value output from said state machine.

11. The method of claim 10 , further comprising the step of:

providing a control voltage to an input of said controlled oscillator for supplying said controlled oscillator with a reference voltage.

12. The method of claim 11 , wherein said control circuit uses said voltage controller to control said second frequency associated with said controlled oscillator.

13. The method of claim 12 , wherein said reference voltage is variably adjusted by said control circuit to adjust said second frequency associated with said controlled oscillator.

14. The method of claim 13 , wherein said control circuit variably adjusts said reference voltage until said frequency difference is within said predetermined acceptable range.

15. The method of claim 10 , further comprising the step of:

providing a control currently to an input of said controlled oscillator for supplying said controlled oscillator with a reference current.

16. The method of claim 15 , wherein said control circuit uses said current controller to control said second frequency associated with said controlled oscillator.

17. The method of claim 16 , wherein said reference current is variably adjusted by said control circuit to adjust said second frequency associated with said controlled oscillator.

18. The method of claim 17 , wherein said control circuit variably adjusts said reference currently until said frequency difference is within said predetermined acceptable range.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2007
From: DAI, XINGDONG; AHMED, YASSER; ABEL, CHRISTOPHER J.; LOGAN, SHAWN MICHAEL
To: AGERE SYSTEMS, INC.
Reel/Frame 020071/0080 →
Continuity (1)
Related Publication 20090115536A1 · May 7, 2009