Systems and methods for improving serviceability of a memory system
View Patent ↗Systems and methods for improving serviceability of a memory system including a method for identifying a failing memory element in a memory system when two or more modules operate in unison in response to a read request. The method includes receiving syndrome bits and an address associated with an uncorrectable error (UE). In response to a previous correctable error (CE) having occurred, the location of the previous CE is retrieved. The location of the CE specifies a memory device position of the CE. A location of the UE is determined using the location of the previous CE and the syndrome bits of the UE as input. The location of the UE specified a memory device position. A failing memory element associated with the location of the UE is identified.
1. A method for identifying a failing memory element in a memory system when two or more memory modules operate in unison in response to a read request, the method comprising:
receiving syndrome bits associated with one symbol correcting code error correction code (ECC) word, the syndrome bits indicating an uncorrectable error (UE); and
in response to one or more previous correctable errors (CEs) having occurred:
retrieving the location of a previous CE, the location of the previous CE specifying a memory module and an address;
determining a location of the UE using the location of the previous CE as input to the determining, the location of the UE specifying a memory device position; and
identifying a failing memory element associated with the location of the UE.
2. The method of claim 1 wherein the failing memory element is a memory device.
3. The method of claim 1 wherein the failing memory element is a memory module.
4. The method of claim 1 further comprising correcting the data read at the location of the UE.
5. The method of claim 1 wherein one or more of the receiving, retrieving, determining, and identifying is performed by a service processor.
6. The method of claim 1 wherein the location of the previous CE is retrieved from non-volatile storage.
7. The method of claim 1 further comprising performing one or more of activating a visual indicator identifying the failing memory element and generating a report indicating the failing memory element.
8. The method of claim 1 further comprising determining the magnitude of one or both of the CE and the UE.
9. The method of claim 1 wherein the retrieving, determining and identifying are performed in response to the previous CE having occurred at the same address range as the address range of the UE, the address range comprised of at least the address included in the location of the previous CE.
10. A method for identifying a failing memory element in a memory system where two or more memory modules operate in unison in response to a read request, the method comprising:
receiving an address associated with an uncorrectable error (UL) and data related to the UE including one or more of syndrome bits associated with one symbol correcting code error correction code (ECC) word and read data; and
in response to one or more previous correctable errors (CEs) having occurred:
retrieving read data related to a previous CE; and
identifying a failing memory element using the read data related to the previous CE and the data related to the UE as input to the identifying.
11. The method of claim 10 wherein the failing memory element is one or more of a memory device and a memory module.
12. The method of claim 10 further comprising correcting the data read at the location of the UE.
13. The method of claim 10 wherein one or more of the receiving, retrieving, and identifying is performed by a service processor.
14. The method of claim 10 wherein the location of the previous CE is retrieved from non-volatile storage.
15. The method of claim 10 further comprising performing one or more of activating a visual indicator identifying the failing memory element and generating a report indicating the failing memory element.
16. The method of claim 10 wherein the retrieving and identifying are performed in response to the previous CE having occurred at the same address range as the address range of the UE, the address range comprised of at least one address.
17. A memory system for identifying a failing memory element, the memory system comprising:
two or more memory modules operating in unison in response to read requests, each memory module including one or more memory devices; and
storage means for storing failure information associated with a first fail at an address; and
a processor including logic for facilitating:
receiving syndrome bits associated with one symbol correcting code error correction code (ECC) word, the syndrome bits indicating an uncorrectable error (UL); and
in response to one or more previous correctable errors (CEs) having occurred:
retrieving the location of a previous CE, the location of the previous CE specifying a memory module and an address;
determining a location of the UE using the location of the previous CE as input to the determining, the location specifying a memory device position; and
identifying a failing memory element associated with the location of the UE.
18. The memory system of claim 17 wherein the retrieving, determining and identifying are performed in response to the previous CE having occurred at the same address range as the address range of the UE, the address range comprising at least one address.
19. The memory system of claim 17 wherein the logic is implemented in one or more of hardware and software.
20. The memory system of claim 17 wherein the logic further enables correcting up to a byte of data read at the location of the UE in response to determining the location of the UE.