Memory controller with programmable regression model for power control

1. A method of managing power usage of a memory device, comprising:

setting a target power consumption for the memory device;

estimating a throttling delay for achieving the target power consumption;

periodically blocking memory commands to one or more selected ranks of the memory device for a number of clock cycles corresponding to the throttling delay; and

powering down the selected ranks while the memory commands are blocked.

2. The method of claim 1 wherein said estimating includes using a regression model which bases the throttling delay on a plurality of operating factors including power consumption, and a plurality of regression coefficients for the operating factors.

3. The method of claim 2 wherein the operating factors further include a current number of bank conflicts for the memory device.

4. The method of claim 2 wherein the operating factors further include a current number of read commands and a current number of write commands for the memory device.

5. The method of claim 2 , further comprising programmably storing the regression coefficients for use with a current system configuration.

6. The method of claim 2 , further comprising calculating the regression coefficients by:

constructing a matrix Φ of training sets for the operating factors resulting in respective throttling delays y; and

computing the regression coefficients β as

β=Φ + y

where Φ + is the pseudo-inverse of Φ.

7. The method of claim 1 wherein all memory ranks of the memory device are block for the number of clock cycles.

8. The method of claim 1 , further comprising:

receiving a plurality of memory commands directed to the memory device;

determining power priorities for the memory commands;

reordering the memory commands for dispatch to the memory device based on the power priorities; and

powering down one or more further selected memory ranks based on rank localities of the reordered commands.

9. A memory controller for a memory device, comprising:

throttling delay logic which estimates a throttling delay for achieving a target power consumption for the memory device;

a scheduler which periodically blocks memory commands to one or more selected ranks of the memory device for a number of clock cycles corresponding to the throttling delay; and

a power-down unit which issues a power-down command to the memory device addressed to the selected memory ranks while the memory commands are blocked.

10. The memory controller of claim 9 wherein said throttling delay logic uses a regression model which bases the throttling delay on a plurality of operating factors including power consumption, and a plurality of regression coefficients for the operating factors.

11. The memory controller of claim 10 wherein the operating factors further include a current number of bank conflicts for the memory device.

12. The memory controller of claim 10 wherein the operating factors further include a current number of read commands and a current number of write commands for the memory device.

13. The memory controller of claim 10 wherein the regression coefficients are programmably stored in said throttling delay logic for use with a current system configuration.

14. The memory controller of claim 10 wherein the regression coefficients are calculated by:

constructing a matrix Φ of training sets for the operating factors resulting in respective throttling delays y; and

computing the regression coefficients β as

β=Φ + y

where Φ + is the pseudo-inverse of Φ.

15. The memory controller of claim 9 wherein said scheduler blocks all memory ranks of the memory device for the number of clock cycles.

16. The memory controller of claim 9 wherein:

said scheduler includes a state machine which determines power priorities for a plurality of memory commands directed to the memory device, and reorders the memory commands for dispatch to the memory device based on the power priorities; and

said power-down unit issues a power-down command to the memory device addressed to one or more further selected memory ranks based on rank localities of the reordered commands.

17. A computer system comprising:

one or more processors which process program instructions;

a memory device connected to said one or more processors; and

a memory controller which estimates a throttling delay for achieving a target power consumption for said memory device, periodically blocks memory commands to one or more selected ranks of said memory device for a number of clock cycles corresponding to the throttling delay, and issues a power-down command to said memory device addressed to the selected memory ranks while the memory commands are blocked.

18. The computer system of claim 17 wherein said memory controller uses a regression model which bases the throttling delay on a plurality of operating factors and a plurality of regression coefficients for the operating factors, the operating factors including:

target power consumption;

a current number of read commands for the memory device;

a current number of write commands for the memory device; and

a current number of bank conflicts for the memory device.

19. The computer system of claim 18 wherein the regression coefficients are programmably stored in said memory controller for use with a current system configuration, and are calculated by:

constructing a matrix Φ of training sets for the operating factors resulting in respective throttling delays y; and

computing the regression coefficients β as

β=Φ + y

where Φ + is the pseudo-inverse of Φ.

20. A method of modeling throttled power consumption of a memory device, comprising:

constructing a matrix Φ of training sets for a plurality of operating factors resulting in respective throttling delays y, wherein the operating factors include power consumption;

computing regression coefficients β for the operating factors as

β=Φ + y

where Φ + is the pseudo-inverse of Φ; and

storing the regression coefficients.