Memory-based trigger generation scheme in an emulation environment
View Patent ↗A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.
1. A method for trigger generation in a hardware emulator, comprising:
receiving a plurality of input probe signals on an address port to a memory from a programmable integrated circuit within the emulator;
outputting, from a data port of the memory, data that is addressed, at least in part, by the input probe signals, the memory being a dual-port memory that is writable in order to configure the data output port; and
using all or a part of the data to form a reduced set of probes or a set of one or more trigger signals.
2. The method of claim 1 , further including inputting the data through combinatorial logic to produce the set of trigger signals and further including detecting the set of one or more trigger signals in a logic analyzer.
3. The method of claim 2 , further including initiating or stopping a trace in the hardware emulator or turning on or off an emulator clock in response to the detection.
4. The method of claim 1 , further including receiving, on the memory address port, state information from a logic analyzer and using the state information in combination with the plurality of input probe signals to address the memory.
5. The method of claim 1 , further including receiving, on the memory address port, phase information regarding the phase of a signal in the emulator and using the phase information in combination with the input probe signals to address the memory.
6. The method of claim 1 , wherein the input probe signals compared to the set of triggers represent a trigger generation scheme and further including writing to the memory in order to reconfigure the trigger generation scheme in the hardware emulator.
7. The method of claim 6 , further including emulating a user design in the emulator and continuing to run the hardware emulator clock and continuing to emulate the design during the reconfiguration.
8. The method of 1 , wherein the integrated circuit is one of an array of programmable circuits within the hardware emulator, the programmable circuits being configured to imitate a user design and wherein the memory is a combination of several independent memory chips.
9. The method of claim 1 , wherein the memory is a first memory that produces the reduced set of probes and further including receiving the reduced set of probes as input signals on an address port to a second memory and outputting from a data port of the second memory one or more trigger signals.
10. The method of claim 9 , further including dynamically reconfiguring the memory of the probe reduction circuit without stopping the emulator clock.
11. A trigger generating apparatus in a hardware emulator, comprising:
a plurality of programmable integrated circuits within the hardware emulator;
a plurality of input probe lines coupled to one or more of the programmable integrated circuits; and
a memory having an address port to which multiple of the input probe lines are connected and a data output port coupled to a reduced set of probes or a set of trigger lines, the memory being a dual-port memory that is writable in order to configure the data output port.
12. The trigger generating apparatus of claim 11 , further including trigger configuration address lines coupled to the address port of the memory, trigger configuration data lines coupled to the data port of the memory, and a trigger configuration write signal coupled to the write input of the memory.
13. The trigger generation apparatus of claim 11 , further including a logic analyzer having inputs coupled either directly to the data output port of the memory for receiving trigger information or indirectly through combinatorial logic.
14. The trigger generation apparatus of claim 11 , further including a trace memory coupled to the logic analyzer and to outputs of the programmable integrated circuits for collecting or terminating trace information from the programmable integrated circuits in response to activation of a trigger.
15. The trigger generation apparatus of claim 11 , further including a logic analyzer having outputs indicating the state of the logic analyzer, the logic analyzer outputs being coupled to the address port of the memory together with the input probe lines.
16. The trigger generation apparatus of claim 11 , further including a hardware emulation host coupled to the hardware emulator, the hardware emulation host coupled to the memory for writing to the memory in order to change a trigger generation scheme.
17. The trigger generation apparatus of claim 11 , wherein the memory is a combination of several different dual-port memory chips.
18. The trigger generation apparatus of claim 11 , wherein the programmable integrated circuits are FPGAs.