Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices
View Patent ↗Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.
1. A field effect transistor, comprising:
a semiconductor substrate;
a silicon oxide layer on said substrate;
a stiffening layer on said silicon oxide layer, said stiffening layer having a Young's modulus greater than that of said silicon oxide layer;
a single crystal silicon layer said stiffening layer;
a source and a drain on opposite sides of a channel region of said silicon layer;
a gate electrode over said channel region; and
a gate dielectric between said gate electrode and said channel region.
2. The transistor of claim 1 , further including:
dielectric isolation extending from a top surface of said silicon layer, through said stiffening layer, to said silicon oxide layer, said dielectric isolation defining a perimeter of a region of said silicon layer containing said source, said drain and said channel region.
3. The transistor of claim 1 , wherein said stiffening layer has a Young's modulus greater than 168 GPa.
4. The transistor of claim 1 , wherein said stiffening layer is in neutral stress or in a stress between about −200 MPa and about 200 MPa.
5. The transistor of claim 1 , further including:
a stress layer formed over said source, said drain and said gate electrode, said stress layer (i) being in compressive stress if said source and drain are doped P-type and said channel region is doped N-type or (ii) being in tensile stress if said source and drain are doped N-type and said channel region is doped P-type.
6. The transistor of claim 1 , wherein said source and said drain do not abut said stiffening layer.
7. The transistor of claim 1 , wherein said source and said drain abut said stiffening layer.
8. The transistor of claim 1 , further including:
strain regions formed in said source and drain, said strain regions extending from a top surface of said silicon layer toward said stiffening layer, regions of said source and drain intervening between said strain regions and said stiffening layer, said strain regions (i) being in compressive stress if said source and drain are doped N-type and said channel region is doped P-type or (ii) being in tensile stress if said source and drain are doped P-type and said channel region is doped N-type.
9. The transistor of claim 8 , wherein said source and said drain do not abut said stiffening layer.
10. The transistor of claim 8 , wherein said source and said drain abut said stiffening layer.
11. A method of fabricating a field effect transistor, comprising:
providing a semiconductor substrate comprising:
a silicon oxide layer on a support substrate;
a stiffening layer on said silicon oxide layer, said stiffening layer having a Young's modulus greater than that of said silicon oxide layer; and
a single crystal silicon layer on said stiffening layer;
forming a source and a drain on opposite sides of a channel region of said silicon layer; and
forming a gate electrode over said channel region and a gate dielectric between said gate electrode and said channel region.
12. The method of claim 11 , further including:
forming dielectric isolation in said semiconductor substrate, said dielectric isolation extending from a top surface of said silicon layer, through said stiffening layer, to said silicon oxide layer, said dielectric isolation defining a perimeter of a region of said silicon layer containing said source, said drain and said channel region.
13. The method of claim 11 , wherein said stiffening layer has a Young's modulus greater than 168 GPa.
14. The method of claim 11 , wherein said stiffening layer is in neutral stress or in a stress between about −200 MPa and about 200 MPa.
15. The method of claim 11 , further including:
forming a stress layer over said source, said drain and said gate electrode, said stress layer (i) being in compressive stress if said source and drain are doped P-type and said channel region is doped N-type or (ii) being in tensile stress if said source and drain are doped N-type and said channel region is doped P-type.
16. The method of claim 11 , wherein said source and said drain do not abut said stiffening layer.
17. The method of claim 11 , wherein said source and said drain abut said stiffening layer.
18. The method of claim 11 , further including:
forming strain regions in said source and drain, said strain regions extending from a top surface of said silicon layer toward said stiffening layer, regions of said source and drain intervening between said strain regions and said stiffening layer, said strain regions (i) being in compressive stress if said source and drain are doped N-type and said channel region is doped P-type or (ii) being in tensile stress if said source and drain are doped P-type and said channel region is doped N-type.
19. The method of claim 18 , wherein said source and said drain do not abut said stiffening layer.
20. The method of claim 18 , wherein said source and said drain abut said stiffening layer.