Granted Patent B2

US 7,737,875 · App. 12/270,609 · Granted Jun 15, 2010

Assignee: NXP B.V.

Abstract

Claims (61)

1. A flash analog-to-digital converter, comprising:

a flash comparator portion to compare an input signal to 2 N −1 reference voltages and to generate 2 N −1 corresponding binary valued comparison signals, wherein adjacent comparison signals represent a given least significant bit quantization level;

a time interpolating encoder to detect a difference in arrival time between a first comparison signal and a second comparison signal from among the binary valued comparison signals and, based on the difference, to generate a voltage interpolation signal capable of encoding a plurality of bins within the given least significant bit quantization level, and capable of identifying which of the bins corresponds to the input signal, wherein the time interpolating decoder includes at least one variable delay unit to delay, based on a feedback control signal, at least one of the first comparison signal and the second comparison signal prior to detecting said difference;

a decoder to generate M-bit output data representing an M-bit quantization of the input signal, wherein M is an integer greater than N, based on the binary valued comparison signals and the voltage interpolation signal;

a feedback control signal generator to generate the feedback control signal, the generator including a code density detector to detect a non-uniformity of a code density of the M-bit output data, wherein the generator generates the control signal based on the detecting.

2. The flash analog-to-digital converter of claim 1 , wherein the time interpolating encoder varies the width of the bins based on the delay of the variable delay unit.

3. The flash analog-to-digital converter of claim 1 , wherein the decoder generates N bits of the M-bit output data based on the 2 N −1 corresponding binary valued comparison signals and K bits of the M-bit output data are based on the voltage interpolation signal, wherein each of the K bits represents a sub-quantization level smaller that said given least significant bit quantization level.

4. The flash analog-to-digital converter of claim 3 ,

wherein there are 2 K of said bins within said given least significant bit quantization level,

wherein said K bits are capable of encoding 2 K states of said 2 K bins,

wherein the feedback control signal generator code density detector includes a counter for counting the uniformity of occurrences among all of the states capable of being represented by the K bits and generating a corresponding counting result, and

wherein the generator generates the control signal based on said counting result.

5. The flash analog-to-digital converter of claim 3 , further comprising:

a multi-level feedback control signal generator for generating, based on said feedback control signal, 2 K−1 −1 lower level feedback control signals, and

wherein said flash comparator portion includes a first signal level comparator to compare, in response to a sample clock, the input signal to a first reference voltage and to generate a corresponding first comparison signal at a first delay time, the first delay time indicative of the difference between the input signal and the first reference voltage, and includes a second signal level comparator to compare, in response to the sample clock, the input signal to a second reference voltage and to generate a corresponding second comparison signal at a second delay time, the second delay time indicative of the difference between the input signal and the second reference voltage,

wherein the time interpolating encoder includes

a first controllable delay for concurrently generating 2 K−1 −1 different delays of said first comparison signal, based on said 2 K−1 −1 lower level feedback control signals,

a second controllable delay for concurrently generating 2 K−1 −1 different delays of said second comparison signal, based on said 2 K−1 −1 lower level feedback control signals,

a multi-level delay time of arrival detector to detect a difference between the first delay time and the second delay time, to detect a difference between the first delay time and a respective occurrence of each of said 2 K−1 −1 different delays of said second comparison signal, and to detect a difference between the second delay time and a respective occurrence of each of said 2 K−1 −1 different delays of said first comparison signal, and based on said detecting, to generate 2 K−1 voltage interpolation signals,

wherein said first comparison signal, said second comparison signal, and said 2 K−1 voltage interpolation signals represent 2 K bins within said least significant bit quantization level.

6. The flash analog-to-digital converter of claim 1 ,

wherein said flash comparator portion includes a first signal level comparator to compare, in response to a sample clock, the input signal to a first reference voltage and to generate a corresponding first comparison signal at a first delay time, the first delay time indicative of the difference between the input signal and the first reference voltage, and includes a second signal level comparator to compare, in response to the sample clock, the input signal to a second reference voltage and to generate a corresponding second comparison signal at a second delay time, the second delay time indicative of the difference between the input signal and the second reference voltage,

wherein the time interpolating encoder includes a first time of arrival detector to detect the difference between the first delay time and the second delay time and to generate, based on said detected difference, a first voltage interpolation signal of said voltage interpolation signals, said first voltage interpolation signal having a binary state representing a sub-quantization level one half of said least significant bit quantization level.

7. The flash analog-to-digital converter of claim 6 , wherein said second signal level comparator is capable of outputting a negative second comparison signal substantially concurrent with said second comparison signal, and

wherein said time interpolating encoder further comprises:

a controllable first delay unit to receive the feedback control signal and the negative second comparison signal and to generate a delayed negative second comparison signal, having a delay relative to said negative second comparison signal based on said delay control signal, and

a second time of arrival detector to detect the difference between the first delay time and an occurrence of the delayed negative second comparison signal, to generate, based on said detected difference, a second voltage interpolation signal of said voltage interpolation signals, said second voltage interpolation signal having a binary state representing a first and a second of a plurality of sub-bins within said second quantization level, each of said sub-bins representing approximately one half of said sub-quantization level.

8. The flash analog-to-digital converter of claim 7 , wherein said time interpolating encoder further comprises:

a controllable second delay unit to receive the feedback control signal and the first comparison signal and to generate a delayed first comparison signal, having a delay relative to said first comparison signal based on said delay control signal, and

a third time of arrival detector to detect the difference between the second delay time and an occurrence of the delayed first comparison signal to generate, based on said detected difference a third voltage interpolation signal of said voltage interpolation signals, said third voltage interpolation signal representing a third and a fourth of said sub-bins.

9. A flash analog-to-digital converting method, comprising:

comparing an input signal to 2 N −1 reference voltages;

generating 2 N −1 corresponding binary valued comparison signals, based on the comparing, wherein adjacent comparison signals represent a given least significant bit quantization level;

detecting a difference in arrival time between a first comparison signal and a second comparison signal from among the binary valued comparison signals and, based on the difference, generating a first-to-arrive signal, wherein the detecting includes delaying at least one of the first comparison signal and the second comparison signal prior to detecting said difference;

generating a voltage interpolation signal capable of encoding a plurality of bins within the given least significant bit quantization level, and capable of identifying which of the bins corresponds to the input signal, said generating based on said first-to-arrive signal;

generating an M-bit output data representing an M-bit quantization of the input signal, based on the binary valued comparison signals and the voltage interpolation signal;

detecting a non-uniformity of a code density of the M-bit output data and generating a corresponding uniformity error data;

generating a feedback control signal based on the uniformity error data; and

varying said delaying based on said feedback control signal.

10. The flash analog-to-digital converting method of claim 9 , wherein said generating a voltage interpolation signal generates said feedback control signal to vary the width of the bins based on the said delay.

11. The flash analog-to-digital converting method of claim 9 , wherein said generating an M-bit output data generates K bits of the M-bit output data based on the voltage interpolation signal.

12. The flash analog-to-digital converting method of claim 11 ,

wherein there are 2 K of said bins within said given least significant bit quantization level,

wherein said K bits are capable of encoding 2 K states of said 2 K bins,

wherein said code density detecting includes counting the uniformity of occurrences among all of the states capable of being represented by the K bits and generating a corresponding counting result, and

wherein said generating the control signal is based on said counting result.

13. The flash analog-to-digital converting method of claim 11 , wherein said generating a feedback control signal includes generating 2 K−1 −1 lower level feedback control signals, and further comprising:

generating 2 K−1 −1 different delays, concurrently, of said first comparison signal, based on said 2 K−1 −1 lower level feedback control signals;

generating 2 K−1 −1 different delays, concurrently, of said second comparison signal, based on said 2 K−1 −1 lower level feedback control signals; and

generating 2 K−1 −1 voltage interpolation signals, said generating based on detecting a difference between the first delay time and the second delay time,

detecting a difference between the first delay time and a respective occurrence of each of said 2 K−1 −1 different delays of said second comparison signal and detecting a difference between the second delay time and a respective occurrence of each of said 2 K−1 −1 different delays of said first comparison signal,

wherein said first comparison signal, said second comparison signal, and said 2 K−1 voltage interpolation signals represent 2K bins within said least significant bit quantization level.

14. The flash analog-to-digital converting method of claim 9 ,

wherein comparing the input signal to 2 N −1 reference voltages includes comparing, in response to a sample clock, the input signal to a first reference voltage, and generating, based on said comparing, a corresponding first comparison signal at a first delay time, the first delay time indicative of the difference between the input signal and the first reference voltage,

comparing, in response to the sample clock, the input signal to a second reference voltage and to generating, based on said comparing, a corresponding second comparison signal at a second delay time, the second delay time indicative of the difference between the input signal and the second reference voltage,

wherein the time interpolating encoding includes detecting the difference between the first delay time and the second delay time, and

generating, based on said detected difference, a first voltage interpolation signal of said voltage interpolation signals, said first voltage interpolation signal having a binary state representing a sub-quantization level one half of said least significant bit quantization level.

15. The flash analog-to-digital converter of claim 14 , wherein said time interpolating encoding further comprises:

generate a delayed first comparison signal, having a delay relative to said first comparison signal based on said feedback control signal,

detecting the difference between the second delay time and an occurrence of the delayed first comparison signal, and

generating, based on said detected difference, a third voltage interpolation signal of said voltage interpolation signals, said third voltage interpolation signal representing a third and a fourth of said sub-bins.

Assignments (11)

Continuity (2)