Delay locked loop circuit

1. A synchronous memory device, comprising:

a delay locked loop (DLL) for receiving a clock signal to generate a DLL clock; and

a clock transferring unit for transferring the clock signal to the DLL in response to a clock enable signal wherein the clock signal is transferred into the DLL when the clock enable signal is enabled and the transferring operation is maintained during a predetermined period after the clock enable signal is disabled.

2. The synchronous memory device of claim 1 , wherein the clock enable signal is enabled according to a power down mode.

3. The synchronous memory device of claim 1 , wherein the clock transferring unit includes:

a clock buffering unit for receiving the clock signal to transfer the received clock signal to the DLL in response to a buffer enable signal; and

a control unit for receiving the clock enable signal to generate the buffer enable signal to the clock buffering unit wherein the buffer enable signal maintains an activation state for the predetermined period after the clock enable signal is inactivated.

4. The synchronous memory device of claim 3 , wherein the control unit includes:

a power down mode controller for generating an internal control signal which determines whether entering a power down mode or exiting the power down mode in response to the clock enable signal; and

a clock edge delay unit for delaying the internal control signal by the predetermined period after the power down mode is entered to generate the buffer enable signal.

5. The synchronous memory device of claim 4 , wherein the clock edge delay unit includes:

a signal delay unit for delaying the internal control signal by the predetermined period; and

a logic unit for receiving an output signal of the signal delay unit to output the output signal as the buffer enable signal.

6. The synchronous memory device of claim 5 , wherein the signal delay unit includes:

a plurality of inverters connected in series; and

a plurality of capacitors connected between the respective inverters.

7. The synchronous memory device of claim 6 , wherein the logic unit includes:

a NAND gate for receiving an output signal of the signal delay unit and the internal control signal; and

an inverter for inverting an output signal of the NAND gate and outputting the inverted signal as the buffer enable signal.

8. The synchronous memory device of claim 7 , wherein the power down mode controller includes:

a first inverter for inverting the clock enable signal;

a NAND gate for receiving an output signal of the first inverter and an idle signal; and

a second inverter for inverting an output signal of the NAND gate to output the inverted signal as the internal control signal.

9. The synchronous memory device of claim 8 , wherein the clock buffer includes:

a differential amplifying unit for generating an internal clock based on the clock signal and an inverted clock signal of the clock signal; and

an output unit for transferring the internal clock in response to the buffer enable signal.

10. The synchronous memory device of claim 9 , wherein the output unit includes:

a first inverter for inverting the buffer enable signal to output an inverted buffer enable signal;

a second inverter for inverting the internal clock to output an inverted output signal;

a transfer gate for transferring the inverted buffer enable signal in response to the internal clock and the inverted output signal;

an inverter chain having a plurality of inverters connected in series, for inverting the internal clock to output a delayed clock signal; and

a NAND gate for performing a logic NAND operation of the inverted the internal clock from the inverter chain and the inverted buffer enable signal transferred from the transfer gate.