IP Library › Granted Patent US 7,757,039
Granted Patent B2
US 7,757,039 · App. 11/901,502 · Granted Jul 13, 2010

DRAM selective self refresh

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Quick Facts
Patent No.
US 7,757,039
App. No.
11/901,502
Granted
Jul 13, 2010
Kind
B2
Abstract

In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Claims (30)

1. A method to manage volatile memory in an electronic device, comprising:

generating a retained page map which indicates memory pages in at least one memory module to be retained in memory;

receiving a signal to alter the operating state of the electronic device to a sleep state;

relocating contents of memory pages in the retained page map from a first location in a memory device to a second location to consolidate the memory pages identified in the retained page map in a subset of memory devices;

generating a page relocation table which indicates the first location and the second location of the contents of the memory pages; and

maintaining the subset of memory devices in a self-refresh sleep state.

2. The method of claim 1 , wherein generating a retained page map which indicates memory pages in at least one memory module to be retained in memory comprises tracking memory pages which have been opened in read-write mode since being retrieved from a non-volatile memory location.

3. The method of claim 1 , wherein generating a retained page map which indicates memory pages in at least one memory module to be retained in memory comprises tracking memory pages which have been updated since being retrieved from a non-volatile memory location.

4. The method of claim 1 , further comprising storing the page relocation table in a memory module.

5. The method of claim 1 , further comprising placing one or more memory devices outside the subset of memory devices into a sleep state in which the memory is not refreshed.

6. The method of claim 1 , further comprising:

receiving a signal to remove the device from a sleep state; and

in response to the signal, restoring the contents of the volatile memory to a state that existed prior to receiving a signal to alter the operating state of the electronic device to a sleep state.

7. The method of claim 6 , wherein restoring the contents of the volatile memory comprises relocating contents of memory pages in the retained page map from the second location back to the first location.

8. An electronic apparatus, comprising:

a processor;

at least one non-volatile memory module;

logic to generate a retained page map which indicates memory pages in at least one memory module to be retained in memory;

logic to receive a signal to alter the operating state of the electronic device to a sleep state;

logic to relocate contents of memory pages in the retained page map from a first location in a memory device to a second location to consolidate the memory pages identified in the retained page map in a subset of memory devices;

logic to generate a page relocation table which indicates the first location and the second location of the contents of the memory pages; and

logic to maintain the subset of memory devices in a self-refresh sleep state.

9. The electronic apparatus of claim 8 , wherein further comprising logic to track memory pages which have been opened in read-write mode since being retrieved from a non-volatile memory location.

10. The electronic apparatus of claim 8 , further comprising logic to track memory pages which have been updated since being retrieved from a non-volatile memory location.

11. The electronic apparatus of claim 8 , further comprising further comprising logic to store the page relocation table in a memory module.

12. The electronic apparatus of claim 8 , further comprising logic to place one or more memory devices outside the subset of memory devices into a sleep state in which the memory is not refreshed.

13. The electronic apparatus of claim 8 , further comprising logic to:

receive a signal to remove the device from a sleep state; and

in response to the signal, restoring the contents of the volatile memory to a state that existed prior to receiving a signal to alter the operating state of the electronic device to a sleep state.

14. The electronic apparatus of claim 13 , further comprising logic to relocate contents of memory pages in the retained page map from the second location back to the first location.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2011
From: KABURLASOS, NIKOS; KARDACH, JIM
To: INTEL CORPORATION
Reel/Frame 025821/0944 →
Continuity (1)
Related Publication 20090077307A1 · Mar 19, 2009