Resistance random access memory and method of manufacturing the same

1. A resistance random access memory comprising:

a lower electrode;

a resistance layer having a metal oxide and a metal ion dopant on the lower electrode, a metal of the metal oxide being different than a metal of the metal ion dopant, the resistance layer configured to be variably resistive according to an applied voltage; and

an upper electrode on the resistance layer.

2. The resistance random access memory of claim 1 , wherein the metal oxide in the resistance layer is NiO.

3. The resistance random access memory of claim 1 , wherein the metal ion dopant in the resistance layer is a transition metal ion.

4. The resistance random access memory of claim 1 , wherein the metal ion dopant in the resistance layer is a Ti ion.

5. The resistance random access memory of claim 1 , wherein the metal ion dopant in the resistance layer is substituted at a metal site of the metal oxide to be bound to oxygen.

6. The resistance random access memory of claim 1 , wherein the metal oxide in the resistance layer is NiO and the metal ion dopant is a Ti ion.

7. The resistance random access memory of claim 1 , wherein the amount of the metal ion dopant in the resistance layer is in the range of about 0.0001-5 wt %.

8. The resistance random access memory of claim 1 , wherein the metal oxide in the resistance layer is at least one oxide selected from the group consisting of a Ni oxide, a Ti oxide, a Hf oxide, a Zr oxide, a Zn oxide, a W oxide, a Co oxide, and a Nb oxide.

9. The resistance random access memory of claim 1 , wherein the metal ion dopant in the resistance layer is at least one ion selected from the group consisting of a Ni ion, a Ti ion, a Hf ion, a Zr ion, a Zn ion, a W ion, a Co ion, and a Nb ion.

10. A method of manufacturing a resistance random access memory, the method comprising:

forming a lower electrode;

forming a resistance layer having a metal oxide and a metal ion dopant on the lower electrode, a metal of the metal oxide being different than a metal of the metal ion dopant, the resistance layer being variably resistive according to an applied voltage; and

forming an upper electrode on the resistance layer.

11. The method of claim 10 , wherein the resistance layer is formed at about room temperature.

12. The method of claim 10 , wherein the metal ion dopant in the resistance layer is substituted at a metal site of the metal oxide to be bound to oxygen.

13. The method of claim 10 , wherein the resistance layer is formed by a deposition using a metal target doped with the metal ion dopant.

14. The method of claim 10 , wherein the resistance layer is formed by a deposition using at least two metal targets.

15. The method of claim 10 , wherein the resistance layer is formed using a sputtering, a chemical vapor deposition (CVD), a plasma vapor deposition (PVD), or an atomic layer deposition (ALD) method.

16. The method of claim 10 , wherein the resistance layer is formed by a deposition using a Ni target doped with a Ti ion.

17. The method of claim 10 , wherein the resistance layer is formed at a temperature in the range from about room temperature to about 200° C.

18. The method of claim 10 , wherein the metal oxide in the resistance layer is at least one oxide selected from the group consisting of a Ni oxide, a Ti oxide, a Hf oxide, a Zr oxide, a Zn oxide, a W oxide, a Co oxide, and a Nb oxide.

19. The method of claim 10 , wherein the metal ion dopant in the resistance layer is at least one ion selected from the group consisting of a Ni ion, a Ti ion, a Hf ion, a Zr ion, a Zn ion, a W ion, a Co ion, and a Nb ion.