Integrated circuit including parylene material layer
An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.
1. An integrated circuit comprising:
a substrate including a contact pad;
a redistribution line coupled to the contact pad;
a dielectric material layer between the substrate and the redistribution line;
a solder ball coupled to the redistribution line;
a parylene material layer hermetically sealing the dielectric material layer and the redistribution line, and
a fan-out area laterally adjacent the substrate, the fan-out area comprising a mold material supporting at least a portion of the redistribution line, the dielectric material layer, and the parylene material layer,
wherein the solder ball is within the fan-out area.
2. The integrated circuit of claim 1 , further comprising:
a solder stop material layer over the parylene material layer.
3. The integrated circuit of claim 1 , wherein the integrated circuit comprises a wafer level package.
4. A wafer comprising:
a mold material supporting a plurality of separated die, each die including a contact pad;
a redistribution line coupled to each contact pad;
a dielectric material layer between each die and each redistribution line;
a solder ball coupled to each redistribution line; and
a parylene material layer sealing each dielectric material layer and each redistribution line,
wherein the mold material provides a fan-out area laterally adjacent each die, the fan-out area supporting at least a portion of the redistribution line, the dielectric material layer, and the parylene material layer, and
wherein the solder ball is within the fan-out area.
5. The wafer of claim 4 , further comprising:
a solder stop material layer over each parylene material layer.
6. The wafer of claim 4 , wherein each parylene material layer provides a hermetic seal.
7. The integrated circuit of claim 1 , wherein a thickness of the parylene material layer is less than a thickness of the redistribution line and less than a thickness of the dielectric material layer.
8. The integrated circuit of claim 2 , wherein a thickness of the parylene material layer is less than a thickness of the solder stop material layer.
9. The wafer of claim 4 , wherein a thickness of each parylene material layer is less than a thickness of each redistribution line and less than a thickness of each dielectric material layer.
10. The wafer of claim 5 , wherein a thickness of each parylene material layer is less than a thickness of each solder stop material layer.