Flash memory device and method of controlling flash memory device
A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
1. A flash memory device comprising:
a plurality of memory blocks;
a decoder configured to select at least one of the plurality of memory blocks in response to block select signals;
a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block;
an output buffer configured to output fixed data in response to the flag signal, indicating that the block address corresponds to the bad block; and
a ready/busy generator configured to output a ready/busy signal in response to the flag signal, indicating that the block address corresponds to the bad block,
wherein, when the block address corresponds to the bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
2. The flash memory device of claim 1 , wherein the decoder has no storage element for storing bad block information.
3. The flash memory device of claim 1 , wherein the controller comprises:
a repair controller configured to generate the flag signal when the block address corresponds to the bad block;
a disable circuit configured to generate a disable signal in response to the flag signal; and
a predecoder configured to generate the block select signals in response to the block address,
wherein the predecoder generates the block select signals to inactivate the bad block when the predecoder receives the disable signal.
4. The flash memory device of claim 1 , wherein the ready/busy generator sets the ready/busy signal to a busy state in response to the flag signal.
5. The flash memory device of claim 1 , wherein the ready/busy generator sets the ready/busy signal to a ready state in response to the flag signal.
6. The flash memory device of claim 1 , further comprising:
a memory for storing the fixed data.
7. The flash memory device of claim 1 , further comprising:
a program/read/erase controller configured to interrupt one of a program/read/erase operation with respect to the memory block corresponding to the block address in response to the flag signal.
8. The flash memory device of claim 1 , further comprising:
a pass/fail detector configured to indicate a fail state in response to the flag signal.
9. The flash memory device of claim 3 , wherein the repair controller further comprises an address register that stores block addresses of bad blocks.
10. A flash memory device comprising:
a cell array comprising a plurality of memory blocks;
a redundant cell array comprising one or more redundant blocks;
a plurality of block decoders, corresponding to the plurality of memory blocks, for selecting corresponding memory blocks in response to block select signals, respectively;
a repair controller for generating the block select signals in response to a block address and for generating a flag signal and a repair signal when the block address corresponds to a bad block; and
a redundant block decoder for activating a redundant block of the one or more redundant blocks when the block address corresponds to a bad block, the redundant block decoder being selected by the repair signal,
wherein each of the plurality of block decoders has no storage element for storing bad block information; and
wherein the block select signals are generated to interrupt selecting the bad block.
11. The flash memory device of claim 10 , wherein the repair controller comprises:
a repair control circuit for generating the flag signal and a repair signal for selecting the redundant block corresponding to the bad block when the block address corresponds to the bad block;
a disable circuit for generating a disable signal in response to the flag signal and the repair signal; and
a predecoder for generating the block select signals in response to the block address,
wherein, when the disable signal is received, the predecoder generates the block select signals to inactivate a memory block corresponding to the block address.
12. The flash memory device of claim 11 , wherein the repair control circuit comprises a memory that stores the bad block address.
13. The flash memory device of claim 11 , wherein the repair control circuit comprises a memory that stores an address of the redundant block.
14. A method of managing a bad block in a flash memory device, comprising a memory block and a block decoder for selecting the memory block in response to a block select signal, the method comprising:
comparing an input block address with a bad block address, which indicates a defective memory block;
generating a flag signal when the input block address corresponds to the bad block address; and
generating a ready/busy signal in response to the flag signal, the ready/busy signal being output externally to indicate that the block address corresponds to the bad block address,
wherein the block decoder does not include a storage element for indicating the defective memory block.
15. The method of claim 14 , further comprising:
outputting fixed data having a predetermined bit value via an input/output pin to indicate that the block address corresponds to the bad block address.
16. The method of claim 14 , further comprising:
interrupting an internal operation corresponding to a command input with the input block address.