Methods of forming phase-changeable memory devices using growth-enhancing and growth-inhibiting layers for phase-changeable materials
Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.
1. A method of forming an integrated circuit memory device, comprising:
forming an interlayer insulating layer having an opening therein, on a substrate;
covering a bottom of the opening and lining sidewalls of the opening and an upper surface of the interlayer insulating layer with a seed layer;
selectively depositing an electrically insulating growth-inhibiting layer on a portion of the seed layer surrounding the opening; and
forming a phase-changeable material region in the opening.
2. The method of claim 1 , wherein the seed layer comprises a transition metal oxide.
3. The method of claim 2 , wherein the transition metal oxide is selected from a group consisting of titanium oxide, zirconium oxide, hafnium oxide and tantalum oxide.
4. The method of claim 3 , wherein forming a phase-changeable material region comprises selectively growing the phase-changeable material region on the seed layer in the opening.
5. The method of claim 3 , wherein forming a phase-changeable material region comprises selectively growing the phase-changeable material region on the seed layer in the opening; and wherein the growth-inhibiting layer comprises a material selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide and aluminum oxide.
6. The method of claim 1 , wherein the phase-changeable material region comprises a chalcogenide material.
7. A method of forming an integrated circuit memory device, comprising:
forming an interlayer insulating layer having an opening therein, on a substrate;
lining sidewalls of the opening with a seed layer;
selectively depositing an electrically insulating growth-inhibiting layer on a portion of the interlayer insulating layer surrounding the opening; and
forming a phase-changeable material region in the opening;
wherein selectively depositing an electrically insulating growth-inhibiting layer comprises sputter depositing the electrically insulating layer onto the interlayer insulating layer at a tilt angle in a range between 20° and 65° relative to a normal to the substrate.
8. A method of forming an integrated circuit memory device, comprising:
forming an interlayer insulating layer having an opening therein, on a substrate;
lining sidewalls of the opening with a seed layer;
selectively depositing an electrically insulating growth-inhibiting layer on a portion of the interlayer insulating layer surrounding the opening; and
forming a phase-changeable material region in the opening;
wherein lining sidewalls of the opening with a seed layer comprises lining sidewalls of the opening and an upper surface of the interlayer insulating layer with a seed layer having a thickness in a range between 10 Å and 30 Å; and
wherein selectively depositing an electrically insulating growth-inhibiting layer comprises sputter depositing the growth-inhibiting layer onto the seed layer at a tilt angle in a range between 20° and 65° relative to a normal to the substrate.
9. A method of forming an integrated circuit memory device, comprising:
forming an interlayer insulating layer having an array of openings therein, on a substrate;
lining sidewalls of the openings and an upper surface of the interlayer insulating layer with a metal oxide seed layer using a blanket deposition technique;
sputter depositing an electrically insulating growth-inhibiting layer onto the metal oxide seed layer at a tilt angle in a range between 20° and 65° relative to a normal to the substrate, to thereby inhibit deposition of the growth-inhibiting layer into the openings; then
filling the openings with respective phase-changeable material regions;
forming upper electrodes on the phase-changeable material regions; and
forming a bit line on a plurality of the upper electrodes.
10. The method of claim 9 , wherein forming an interlayer insulating layer comprises forming an interlayer insulating layer having an array of openings therein that respectively include a lower electrode at a bottom of the opening; and wherein said lining comprises covering the lower electrodes at the bottoms of the openings with the metal oxide seed layer.
11. The method of claim 10 , wherein the metal oxide seed layer comprises a metal oxide selected from a group consisting of titanium oxide, zirconium oxide, hafnium oxide and tantalum oxide.
12. The method of claim 11 , wherein the metal oxide seed layer has a thickness in a range between 10 Å and 30 Å.
13. The method of claim 9 , wherein the metal oxide seed layer has a thickness in a range between 10 Å and 30 Å.
14. The method of claim 9 , wherein filling the openings with respective phase-changeable material regions comprises growing phase-changeable material regions from portions of the metal oxide seed layer that are not covered by the growth-inhibiting layer.
15. The method of claim 9 , wherein the growth-inhibiting layer comprises at least one material selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide and aluminum oxide.
16. The method of claim 10 , wherein forming an interlayer insulating layer is preceded by forming an electrically insulating layer having an array of diodes therein, between the interlayer insulating layer and the substrate; and wherein the lower electrodes in the interlayer insulating layer are aligned with corresponding ones of the diodes in the array of diodes.
17. A method of forming an integrated circuit memory device, comprising:
forming an electrically conductive word line in a semiconductor substrate;
forming a first interlayer insulating layer having a first opening therein that extends opposite the word line, on the semiconductor substrate;
forming a P-N junction diode having a diode electrode thereon, in the first opening;
forming a second interlayer insulating layer having a second opening therein that exposes the diode electrode, on the first interlayer insulating layer;
depositing a transition metal oxide seed layer having a thickness in a range between 10 Å and 30 Å onto the second interlayer insulating layer and onto sidewalls of the second opening;
covering portions of the transition metal oxide seed layer extending outside the second opening by sputter depositing an electrically insulating growth-inhibiting layer onto the metal oxide seed layer at a non-zero tilt angle relative to a normal to the substrate; then
filling the second opening with a phase-changeable material region by growing the phase-changeable material region from portions of the metal oxide seed layer within the second opening; and
forming an upper electrode on the phase-changeable material region.
18. The method of claim 17 , wherein depositing a transition metal oxide seed layer is preceded by a step of forming a lower electrode at a bottom of the second opening, which is electrically connected to the diode electrode.
19. The method of claim 17 , wherein the transition metal oxide seed layer comprises a material selected from a group consisting of titanium oxide, zirconium oxide, hafnium oxide and tantalum oxide.
20. The method of claim 17 , wherein the tilt angle is greater than 20°.