Semiconductor device including single crystal silicon layer
A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>. The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.
1. A semiconductor device comprising:
a P-MOS (P-type metal oxide semiconductor) single crystal TFT (thin film transistor); and
an N-MOS (N-type metal oxide semiconductor) single crystal TFT, wherein the P-MOS single crystal TFT and the N-MOS single crystal TFT are sequentially stacked.
2. The semiconductor device of claim 1 , further comprising:
a substrate, wherein the P-MOS single crystal TFT is formed on the substrate, and the N-MOS single crystal TFT is formed on the P-MOS single crystal TFT.
3. The semiconductor device of claim 2 , wherein a source region of the P-MOS single crystal TFT and a source region of the N-MOS single crystal TFT are connected to each other.
4. The semiconductor device of claim 3 , wherein the P-MOS single crystal TFT and the N-MOS single crystal TFT share a common gate.
5. The semiconductor device of claim 2 , wherein the P-MOS single crystal TFT includes a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>.
6. The semiconductor device of claim 5 , wherein the N-MOS single crystal TFT includes a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having greater tensile stress than the single crystal silicon layer of the P-MOS single crystal TFT.
7. The semiconductor device of claim 2 , wherein the substrate is formed of one of SOI (silicon on insulator), glass, and plastic.
8. The semiconductor device of claim 1 , wherein the semiconductor device is an SRAM (static random access memory), the P-MOS single crystal TFT is a pull-up TFT, the N-MOS single crystal TFT is a pull-down TFT, the SRAM further comprising:
a substrate; and
a pass TFT formed on the substrate.
9. The semiconductor device of claim 8 , wherein the P-MOS single crystal TFT and the N-MOS single crystal TFT share a common gate.
10. The semiconductor device of claim 8 , wherein the P-MOS single crystal TFT includes a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>.
11. The semiconductor device of claim 10 , wherein the N-MOS single crystal TFT includes a single crystal silicon layer having a same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having greater tensile stress than the single crystal silicon layer of the P-MOS single crystal TFT.
12. The semiconductor device of claim 8 , wherein the substrate is formed of one of SOI, glass, and plastic.
13. The semiconductor device of claim 1 , wherein the semiconductor device is a logic device.
14. The semiconductor device of claim 13 , wherein the P-MOS single crystal TFT and the N-MOS single crystal TFT share a common gate.
15. The semiconductor device of claim 13 , wherein the P-MOS single crystal TFT includes a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>.
16. The semiconductor device of claim 15 , wherein the N-MOS single crystal TFT includes a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.
17. The semiconductor device of claim 13 , wherein a substrate is formed of one of SOI, glass, and plastic.
18. A flat panel display device comprising:
a system chip mounted on a flat display panel, the system chip including the semiconductor device according to claim 1 .
19. The flat panel display device of claim 18 , wherein the P-MOS single crystal TFT and the N-MOS single crystal TFT share a common gate.
20. The flat panel display device of claim 18 , wherein the P-MOS single crystal TFT includes a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>.
21. The flat panel display device of claim 20 , wherein the N-MOS single crystal TFT includes a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.
22. The flat panel display device of claim 18 , wherein the semiconductor device includes a substrate formed of one of SOI, glass, and plastic.