Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators

1. A phase-locked loop (PLL) circuit, comprising:

a digitally controlled oscillator (DCO) circuit to generate a DCO output signal in response to an n-bit digital frequency control signal comprising an integer portion and a fractional portion;

a dithering circuit that encodes the fractional portion of the digital frequency control signal to generate dithering control signals (DITH); and

a pulse width modulation circuit that uses the DITH signal and the DCO output signal to generate pulse width modulated dither control signals, wherein the pulse width modulated dither control signals are input to a dithered fractional frequency control port of the DCO to drive frequency dithering tuning elements.

2. The PLL circuit of claim 1 , wherein the dithering circuit is a sigma delta modulation circuit.

3. The PLL circuit of claim 1 , comprising a digital loop filter that generates the n-bit digital frequency control signal, wherein the integer portion is directly input to an integer tracking input control port of the DCO.

4. The PLL circuit of claim 1 , wherein the pulse width modulation circuit comprises:

a series of frequency divider circuits which generate a plurality of divided oscillator clock signals from the DCO output signal, and

a logic encoder that encodes the divided oscillator clock signals and the DCO output signal to generate the pulse width modulated dither control signals.

5. The PLL circuit of claim 1 , wherein the pulse width modulation circuit comprises:

a phase rotator;

an exclusive-OR (XOR) logic circuit; and

an AND logic circuit,

wherein the phase rotator receives clock inputs comprising quadrature signals C 1 _ 0 and C 1 _ 90 wherein C 1 _ 0 is the DCO output signal and C 1 _ 90 is the DCO output signal phase-shifted by 90 degrees, and incrementally applies one of a positive and a negative phase shift to the DCO output signal in response to a phase select control signal and generates a phase shifted clock signal (CROT),

wherein the XOR circuit combines one of the signal C 1 _ 0 and the signal C 1 _ 90 with the CROT signal to generate a modulating signal (CPWM) with a variable pulse width, and

wherein the CPWM and DITH signals are input to the AND logic circuit and logically ANDed to generate the pulse width modulated dither signal.

6. The PLL circuit of claim 1 , wherein the pulse width modulation circuit comprises:

a delayed lock loop circuit that receives as input the DCO output signal and DITH signal and outputs a delayed DCO output signal; and

an exclusive-OR (XOR) logic circuit that receives as input the DCO output signal and delayed DCO output signal and exclusively Ors said input signals to generate the generate the pulse width modulated dither signal.

7. The PLL circuit of claim 6 , wherein the delayed lock loop circuit comprises:

a phase detector that compares phases of the DCO output signal and the delayed DCO output signal;

a loop filter that filters an output of the phase detector;

a delay line that receives as input the DCO output signal and which is driven by an output signal of the loop filter to generate a plurality of delayed versions of the DCO output signal;

a multiplexer; and

an encoder that encodes the DITH signals and generates a multiplexer control signal to drive the multiplexer to output a selected one of the delayed versions of the DCO output signal.

8. A method for frequency tuning a digitally controlled oscillator (DCO) circuit that generates a DCO output signal, comprising:

generating a DCO output signal in response to an n-bit digital frequency control signal comprising an integer portion and a fractional portion;

encoding the fractional portion of the digital frequency control signal to generate dithering control signals (DITH); and

generating pulse width modulated dither control signals using the DCO output signal and the DITH signal; and

driving frequency dithering tuning elements of the DCO using the pulse width modulated dither control signals.

9. The method of claim 8 , wherein the fractional portion of the digital frequency control signal is encoded using a delta-sigma modulation circuit.

10. The method of claim 8 , comprising generating the n-bit digital frequency control signal using a digital loop filter.

11. The method of claim 8 , wherein generating a pulse width modulated dither control signals using the DCO output signal and the DITH signal comprises:

generating a plurality of divided oscillator clock signals from the DCO output signal, and

encoding the divided oscillator clock signals and the DCO output signal to generate the pulse width modulated dither control signals.

12. The method of claim 8 , wherein generating a pulse width modulated dither control signals using the DCO output signal and the DITH signal comprises:

generating a phase shifted control signal (CROT) by phase shifting the DCO output signal;

exclusively ORing the DCO output signal with the CROT signal to generate a modulating signal (CPWM) with a variable pulse width, and

logically ANDing the DITH and CPWM signals to generate the pulse width modulated dither signal.

13. The method of claim 8 , wherein generating a pulse width modulated dither control signals using the DCO output signal and the DITH signal comprises:

generating a delayed DCO output signal in response to an encoded DITH signal; and

exclusively ORing the delayed DCO output signal and the DCO output signal to generate the pulse width modulated dither signal.

14. The method of claim 13 , wherein generating a delayed DCO output signal comprises:

comparing phases of the DCO output signal and the delayed DCO output signal;

filtering a comparison result;

driving a delay line using the filtered comparison result to generate a plurality of delayed versions of the DCO output signal;

encoding the DITH signals to generate a multiplexer control signal; and

driving a multiplexer using the encoded DITH signal to output a selected one of the delayed versions of the DCO output signal.