Increased sensitivity and reduced offset variation in high data rate HSSI receiver
Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
1. A single-stage buffer circuit comprising:
a first differential input transistor and a second differential input transistor, each transistor having a respective gate, source, and drain;
a first input connected to the gate of the first differential input transistor;
a second input connected to the gate of the second differential input transistor;
a first output connected to the drain of the first differential input transistor;
a second output connected to the drain of the second differential input transistor;
a first load resistor connected between the drain of the first differential input transistor and a power supply;
a second load resistor connected between the drain of the second differential input transistor and the power supply;
a first tail current source connected between the source of the first differential input transistor and ground;
a second tail current source connected between the source of the second differential input transistor and ground;
a degeneration resistor connected between the source of the first differential input transistor and the source of the second differential input transistor; and
an equalization capacitor connected between the source of the first differential input transistor and the source of the second differential input transistor; wherein:
at least one of said first and second tail current sources, said degeneration resistor and said first and second load resistors is a variable-valued circuit element.
2. The buffer circuit of claim 1 wherein the at least one variable-valued circuit element further provides the buffer circuit with variable bandwidth.
3. The buffer circuit of claim 1 wherein the buffer circuit is connected as an input buffer to a high speed serial interface (HSSI) receiver.
4. The buffer circuit of claim 3 wherein the buffer circuit is an equalization cell.
5. The buffer circuit of claim 3 wherein the buffer circuit provides a pair of differential serial data signals to the HSSI receiver.
6. A single-stage buffer circuit comprising:
a first differential input transistor and a second differential input transistor, each transistor having a respective gate, source, and drain;
a first input connected to the gate of the first differential input transistor;
a second input connected to the gate of the second differential input transistor;
a first output connected to the drain of the first differential input transistor;
a second output connected to the drain of the second differential input transistor;
a first load resistor connected between the drain of the first differential input transistor and a power supply;
a second load resistor connected between the drain of the second differential input transistor and the power supply;
a first tail current source connected between the source of the first differential input transistor and ground;
a second tail current source connected between the source of the second differential input transistor and ground; and
a degeneration resistor connected between the source of the first differential input transistor and the source of the second differential input transistor; wherein:
the first differential input transistor and the second differential input transistor have a transistor mismatch offset variation; and
the at least one variable-valued circuit element is calibrated to minimize the offset variation.
7. The buffer circuit of claim 6 wherein the at least one variable-valued circuit element further provides the buffer circuit with variable bandwidth.
8. The buffer circuit of claim 6 wherein the buffer circuit is connected as an input buffer to a high speed serial interface (HSSI) receiver.
9. The buffer circuit of claim 8 wherein the buffer circuit is an equalization cell.
10. The buffer circuit of claim 8 wherein the buffer circuit provides a pair of differential serial data signals to the HSSI receiver.
11. A single-stage buffer circuit comprising:
a first differential input transistor and a second differential input transistor, each transistor having a respective gate, source, and drain;
a first input connected to the gate of the first differential input transistor;
a second input connected to the gate of the second differential input transistor;
a first output connected to the drain of the first differential input transistor;
a second output connected to the drain of the second differential input transistor;
a first load resistor connected between the drain of the first differential input transistor and a power supply;
a second load resistor connected between the drain of the second differential input transistor and the power supply;
a first tail current source connected between the source of the first differential input transistor and ground;
a second tail current source connected between the source of the second differential input transistor and ground; and
a degeneration resistor connected between the source of the first differential input transistor and the source of the second differential input transistor; wherein:
the first tail current source and the second tail current source are calibrated to provide constant common mode.
12. The buffer circuit of claim 11 wherein the at least one variable-valued circuit element further provides the buffer circuit with variable bandwidth.
13. The buffer circuit of claim 11 wherein the buffer circuit is connected as an input buffer to a high speed serial interface (HSSI) receiver.
14. The buffer circuit of claim 13 wherein the buffer circuit is an equalization cell.
15. The buffer circuit of claim 13 wherein the buffer circuit provides a pair of differential serial data signals to the HSSI receiver.