Semiconductor device having vertical transistor and method of fabricating the same

1. A method of fabricating a semiconductor device comprising:

preparing a semiconductor substrate comprising a cell region and a peripheral circuit region;

forming island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction on the substrate of the cell region, each of the vertical gate structures comprising a semiconductor pillar having a concave portion formed in a sidewall of the semiconductor pillar and a cell gate electrode surrounding a center portion of the semiconductor pillar in the concave portion of the semiconductor pillar;

simultaneously forming a bit line separation trench inside the semiconductor substrate below a gap region between the vertical gate structures and a peripheral circuit trench confining a peripheral circuit active region inside the semiconductor substrate of the peripheral circuit region, in which the bit line separation trench is formed in parallel with the column direction of the vertical gate structures;

forming a bit line separation insulating layer and a peripheral circuit isolation layer inside the bit line separation trench and the peripheral circuit trench, respectively; and

forming a word line on the bit line separation insulating layer along the row direction of the vertical gate structures, the word line being formed to contact a portion of a sidewall of the cell gate electrode and expose a remaining portion of the sidewall of the cell gate electrode in the column direction of the vertical gate structures and to electrically connect two neighboring vertical gate structures.

2. The method according to claim 1 , wherein the forming of the vertical gate structures comprises:

etching the semiconductor substrate of the cell region by a predetermined depth, thereby forming island-shaped preliminary semiconductor pillars respectively corresponding to the vertical gate structures;

isotropically etching lower portions of the preliminary semiconductor pillars selectively, thereby forming the semiconductor pillar corresponding to each of the vertical gate structures, an upper width of the semiconductor pillar being greater than a lower width thereof thereby forming the concave portion;

forming a cell gate electrode layer filling a gap region between the semiconductor pillar and a neighboring semiconductor pillar; and

unisotropically etching the cell gate electrode layer, thereby forming the cell gate electrode corresponding to each of the semiconductor pillars.

3. The method according to claim 1 , before forming the bit line separation trench and the peripheral circuit trench, the method further comprising forming an impurity region inside the semiconductor substrate below the gap region between the vertical gate structures of the cell region, in which the impurity region is separated by the bit line separation trench during the formation of the bit line separation trench and the peripheral circuit trench, thereby forming a drain region.

4. The method according to claim 1 , before forming the vertical gate structures, the method further comprising forming a surface impurity region on a surface of the semiconductor substrate of the cell region, in which the surface impurity region is separated during the formation of the vertical gate structures, and remaining inside upper portions of the vertical gate structures so as to function as a source region.

5. The method according to claim 1 , after forming the word line, the method further comprising forming a source region inside an upper portion of the semiconductor pillar.

6. The method according to claim 1 , wherein the gap region between the vertical gate structures comprises a first gap region between the vertical gate structures aligned along the row direction and a second gap region between the vertical gate structures aligned along the column direction, and the first gap region is formed to have a greater width than that of the second gap region.

7. The method according to claim 6 , wherein the forming of the bit line separation trench and the peripheral circuit trench comprises:

forming a spacer covering sidewalls of the first gap region, and a spacer layer pattern filling the second gap region; and

etching the semiconductor substrate below the first gap region on which the spacer is formed and a predetermined portion of the semiconductor substrate of the peripheral circuit region.

8. The method according to claim 7 , wherein the forming of the bit line separation insulating layer and the peripheral circuit isolation layer comprises:

forming an isolation insulating layer on the substrate having the bit line separation trench and the peripheral circuit trench;

planarizing the isolation insulating layer until upper surfaces of the vertical gate structures and an upper surface of the semiconductor substrate of the peripheral circuit region are exposed, thereby forming a peripheral circuit isolation layer in the peripheral circuit region; and

selectively etching the planarized isolation insulating layer on the bit line separation trench and the spacer, thereby forming a bit line separation insulating layer covering the bit line separation trench and extending to a portion between the vertical gate structures.

9. The method according to claim 1 , wherein the forming of the bit line separation trench and the peripheral circuit trench comprises:

forming a mask insulating layer filling a gap region between the vertical gate structures;

selectively etching the mask insulating layer, thereby forming a mask insulating layer groove exposing the semiconductor substrate below the gap region between the vertical gate structures in a column direction; and

etching the semiconductor substrate exposed by the mask insulating layer groove and a predetermined portion of the semiconductor substrate of the peripheral circuit region.

10. The method according to claim 9 , wherein the forming of the bit line separation insulating layer and the peripheral circuit isolation layer comprises:

forming an isolation insulating layer on the substrate having the bit line separation trench and the peripheral circuit trench;

planarizing the isolation insulating layer until upper surfaces of the vertical gate structures and an upper surface of the semiconductor substrate of the peripheral circuit region are exposed, thereby forming a peripheral circuit isolation layer in the peripheral circuit region; and

selectively etching the planarized isolation insulating layer and the mask insulating layer on the bit line separation trench, thereby forming a bit line separation insulating layer covering the bit line separation trench, and extending to and filling a predetermined portion between the vertical gate structures.

11. The method according to claim 1 , wherein the bit line separation trench is formed to have a smaller width than a distance between the vertical gate structures aligned along the row direction.

12. The method according to claim 1 , after forming the word line, the method further comprising:

forming an insulating layer on the word line to fill the gap region between the vertical gate structures;

forming a conductive layer on the substrate having the insulating layer; and

patterning the conductive layer, thereby forming contact pads covering respective upper surfaces of the vertical gate structures, and a peripheral circuit gate electrode crossing the peripheral circuit active region on the semiconductor substrate of the peripheral circuit region.

13. The method according to claim 12 , further comprising implanting impurity ions into the semiconductor substrate, using the contact pads and the peripheral circuit gate electrode as ion implantation masks, thereby forming peripheral circuit source and drain regions inside the semiconductor substrate of the peripheral circuit region.

14. The method according to claim 13 , further comprising:

forming an interlayer insulating layer on the substrate having the peripheral circuit source and drain regions; and

forming buried contact plugs and peripheral circuit contact plugs through the interlayer insulating layer so as to be electrically connected to the contact pads and the peripheral circuit source and drain regions, respectively.

15. The method according to claim 14 , further comprising forming cell capacitors electrically connected to the buried contact plugs respectively on the substrate having the buried contact plugs.