IP Library Granted Patent US 7,786,799
Granted Patent B2
US 7,786,799 · App. 12/053,534 · Granted Aug 31, 2010

Trimming technique for high voltage amplifiers using floating low voltage structures

Assignee: Cirrus Logic, Inc.
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Quick Facts
Patent No.
US 7,786,799
App. No.
12/053,534
Granted
Aug 31, 2010
Kind
B2
Abstract

The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.

Claims (60)

1. A circuit system comprising at least one amplifier, the system comprising:

a first MOS transistor having a first source element, a first drain element, and a first gate element;

a first low voltage current source having two ends, at least one of the ends connected to at least one of the MOS transistor elements; and

at least one first Zener clamp connected between the first gate element and at least one other of the first MOS transistor elements, wherein the first Zener clamp comprises a pair of unidirectional Zener diodes in series.

2. The system of claim 1 , further comprising

a second MOS transistor having a second source element, a second drain element, and a second gate element, the second MOS transistor connected to the first MOS transistor;

a second low voltage current source having two ends, at least one of the second low voltage current source ends connected to at least one of the second MOS transistor elements; and

at least one second Zener clamp connected between the second gate element and at least one other of the second MOS transistor elements.

3. The system of claim 2 , wherein at least one component is connected between the second low voltage current source and the first MOS transistor and at least one component is connected between the first low voltage current source and the second MOS transistor.

4. The system of claim 1 , wherein the amplifier is an operational transconductance amplifier.

5. The system of claim 1 , wherein the amplifier is a differential amplifier.

6. The system of claim 1 , wherein the first MOS transistor and the second MOS transistor are substantially imperfectly matched high voltage MOS transistors.

7. A circuit system comprising at least one amplifier, the system comprising:

a first MOS transistor having a first source element, a first drain element, and a first gate element;

a first low voltage current source having two ends, at least one of the ends connected to at least one of the MOS transistor elements;

at least one first Zener clamp connected between the first gate element and at least one other of the first MOS transistor elements; and

a third MOS transistor having a third source element, a third drain element, and a third gate element, wherein at least two of the third MOS transistor elements are connected to two of the ends of the first low voltage current source.

8. The system of claim 7 , further comprising:

a second MOS transistor having a second source element, a second drain element, and a second gate element, the second MOS transistor connected to the first MOS transistor;

a second low voltage current source having two ends, the second low voltage current source connected between at least two of the second MOS transistor elements;

at least one second Zener clamp connected between at least two of the second MOS transistor elements; and

a fourth MOS transistor having a fourth source element, a fourth drain element, and a fourth gate element, at least two of the fourth MOS transistor elements connected to two of the ends of the second low voltage current source.

9. The system of claim 8 , wherein the third MOS transistor and the fourth MOS transistor are high voltage MOS transistors thereby being operable at greater than 5 volts.

10. The system of claim 1 , further comprising

a second MOS transistor having a second source element, a second drain element, and a second gate element, wherein the first MOS transistor and the second MOS transistor are parts of a single amplifier;

a second low voltage current source having two ends, at least one of the second low voltage current source ends connected to one of the second MOS transistor elements; and

at least one second Zener clamp connected between at least two of the second MOS transistor elements,

wherein the MOS transistors are rated for greater than 100 volts.

11. A method for trimming at least one amplifier in a circuit, the method comprising the steps of:

arranging a first MOS transistor having a first source element, a first drain element, and a first gate element in communication with a first low voltage current source having two ends;

connecting at least one first Zener clamp to at least two of the first MOS transistor elements, wherein the first Zener clamp comprises a pair of unidirectional Zener diodes in series; and

manipulating the current source to alter a current across the first MOS transistor.

12. The method of claim 11 , further comprising

connecting a second MOS transistor, having a second source element, a second drain element, and a second gate element, to the first MOS transistor;

connecting a second low voltage current source to the second MOS transistor; and

connecting at least one second Zener clamp to at least two of the second MOS transistor elements.

13. The method of claim 12 , further comprising the step of imperfectly matching the first MOS transistor and the second MOS transistor, wherein the first MOS transistor and the second MOS transistor are high voltage MOS transistors.

14. The method of claim 11 , further comprising the step of connecting a third MOS transistor having a third source element, a third drain element, and a third gate element, to the ends of the first low voltage current source.

15. A method for trimming at least one amplifier in a circuit, the method comprising the steps of:

arranging a first MOS transistor having a first source element, a first drain element, and a first gate element in communication with a first low voltage current source having two ends;

connecting at least one first Zener clamp to at least two of the first MOS transistor elements;

manipulating the current source to alter a current across the first MOS transistor;

connecting a third MOS transistor having a third source element, a third drain element, and a third gate element, to the ends of the first low voltage current source;

arranging a second MOS transistor, having a second source element, a second drain element, and a second gate element, in an amplifier with the first MOS transistor;

connecting a second low voltage current source to the second MOS transistor;

connecting at least one second Zener clamp to at least two of the second MOS transistor elements; and

connecting at least two elements of a fourth MOS transistor having a fourth source element, a fourth drain element, and a fourth gate element, to the ends of the second low voltage current source.

16. The method of claim 15 , further comprising the step of connecting the third MOS transistor and the fourth MOS transistor with a third current source.

17. The method of claim 11 , further comprising:

arranging a second MOS transistor, having a second source element, a second drain element, and a second gate element, in an amplifier with the first MOS transistor;

connecting a second low voltage current source to the second MOS transistor; and

connecting at least one second Zener clamp to at least two of the second MOS transistor elements.

18. A circuit system comprising at least one amplifier, the system comprising:

a first MOS transistor having a first source element, a first drain element, and a first gate element;

a first low voltage current source having two ends, the ends connected to the first source element and the first gate element;

a first electrical device in parallel with the first low voltage current source, wherein the electrical device limits a voltage across the first low voltage current source;

a second MOS transistor having a second source element, a second drain element, and a second gate element, wherein the first MOS transistor and the second MOS transistor are parts of the amplifier;

a second low voltage current source having two ends, the ends connected to the second source element and the second gate element; and

a second electrical device in parallel with the second low voltage current source, wherein the electrical device limits a voltage across the second low voltage current source.

19. The system of claim 18 , wherein the first electrical device and the second electrical device are Zener clamps.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Feb 4, 2014
From: ALLIANCE BANK OF ARIZONA, A DIVISION OF WESTERN ALLIANCE BANK
To: APEX MICROTECHNOLOGY, INC.
Reel/Frame 032130/0456 →
RELEASE OF SECURITY INTEREST Recorded Feb 4, 2014
From: FIDUS MEZZANINE CAPITAL, L.P.
To: APEX MICROTECHNOLOGY, INC.
Reel/Frame 032130/0611 →
SECURITY AGREEMENT Recorded Aug 17, 2012
From: APEX MICROTECHNOLOGY, INC.
To: ALLIANCE BANK OF ARIZONA, A DIVISION OF WESTERN ALLIANCE BANK
Reel/Frame 028802/0520 →
SECURITY AGREEMENT Recorded Aug 17, 2012
From: APEX MICROTECHNOLOGY, INC.
To: FIDUS MEZZANINE CAPITAL, L.P.
Reel/Frame 028802/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2012
From: CIRRUS LOGIC, INC.
To: APEX MICROTECHNOLOGY, INC.
Reel/Frame 028807/0848 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2010
From: BHATTACHARYA, ANINDYA; COX, DAVID F.
To: CIRRUS LOGIC, INC.
Reel/Frame 024389/0280 →
Continuity (1)
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