IP Library Granted Patent US 7,791,075
Granted Patent B2
US 7,791,075 · App. 12/201,130 · Granted Sep 7, 2010

Display device and manufacturing method thereof

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 7,791,075
App. No.
12/201,130
Granted
Sep 7, 2010
Kind
B2
Abstract

A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region.

Claims (46)

1. A display device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a microcrystalline semiconductor film over the gate insulating film, comprising a channel formation region;

a channel protective layer over and in contact with the channel formation region;

a source region over the channel protective layer and over and in contact with the microcrystalline semiconductor film;

a drain region over the channel protective layer and over and in contact with the microcrystalline semiconductor film;

a source electrode over the source region; and

a drain electrode over the drain region,

wherein the channel formation region comprises a doped region to which an impurity element is doped,

wherein the impurity element imparts either p-type conductivity or n-type conductivity to the microcrystalline semiconductor film,

wherein the doped region does not overlap with the source electrode, and

wherein the doped region does not overlap with the drain electrode.

2. The display device according to claim 1 ,

wherein the p-type conductivity or the n-type conductivity imparted by the impurity element is an opposite conductivity type of the source region and the drain region.

3. The display device according to claim 1 , further comprising:

a pixel electrode electrically connected to any one of the source electrode and the drain electrode, and

an insulating film formed to cover a part of the pixel electrode.

4. The display device according to claim 1 , further comprising:

a pixel electrode electrically connected to any one of the source electrode and the drain electrode, and

an insulating film formed between the pixel electrode and the one of the source electrode and the drain electrode.

5. The display device according to claim 1 ,

wherein the microcrystalline semiconductor film is island-shaped.

6. A display device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a microcrystalline semiconductor film over the gate insulating film, comprising a channel formation region;

a channel protective layer over and in contact with the channel formation region;

a source region over the channel protective layer and over and in contact with the microcrystalline semiconductor film;

a drain region over the channel protective layer and over and in contact with the microcrystalline semiconductor film;

a source electrode over the source region; and

a drain electrode over the drain region,

wherein the channel formation region comprises a doped region to which an impurity element is doped, a first non-doped region which is not doped with the impurity element and a second non-doped region which is not doped with the impurity element,

wherein the impurity element imparts either p-type conductivity or n-type conductivity to the microcrystalline semiconductor film,

wherein the first non-doped region is formed between the doped region and the source region, and

wherein the second non-doped region is formed between the doped region and the drain region.

7. The display device according to claim 6 ,

wherein the p-type conductivity and the n-type conductivity imparted by the impurity element is an opposite conductivity type of the source region and the drain region.

8. The display device according to claim 6 , further comprising:

a pixel electrode electrically connected to any one of the source electrode and the drain electrode, and

an insulating film formed to cover a part of the pixel electrode.

9. The display device according to claim 6 , further comprising:

a pixel electrode electrically connected to any one of the source electrode and the drain electrode, and

an insulating film formed between the pixel electrode and the one of the source electrode and the drain electrode.

10. The display device according to claim 6 ,

wherein the microcrystalline semiconductor film is island-shaped.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2008
From: KOBAYASHI, SATOSHI; KAWAMATA, IKUKO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 021460/0925 →
Priority Claims (1)
JP 2007-232667 · Sep 7, 2007 · national
Continuity (1)
Related Publication 20090065784A1 · Mar 12, 2009