Etching solution for multiple layer of copper and molybdenum and etching method using the same
View Patent ↗An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.
1. An etching method for a multiple layer of copper and molybdenum, comprising:
forming the multiple layer of copper and molybdenum on a substrate;
forming a photoresist pattern on the multiple layer; and
etching the multiple layer with an etching solution including: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.
2. The method according to claim 1 , wherein the multiple layer is a double layer including a lower molybdenum layer and an upper copper layer.
3. The method according to claim 2 , wherein the upper copper layer is thicker than the lower molybdenum layer.
4. The method according to claim 1 , wherein the substrate is a glass substrate for a liquid crystal display device.
5. The method according to claim 1 , wherein the multiple layer is used as a data line for a liquid crystal display device.
6. A method for fabricating an array substrate for a liquid crystal display device, comprising:
forming a gate electrode and a gate line on a substrate;
forming a semiconductor layer on the gate electrode and the gate line; and
forming source and drain electrodes on the semiconductor layer and a data line crossing the gate line, wherein at least one of the gate line and the data line is a multiple layer of copper and molybdenum, and etching of the multiple layer is performed with an etching solution including: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and about 45% to about 93.89% by weight of de-ionized water.
7. The method according to claim 6 , wherein the multiple layer is a double layer including a lower molybdenum layer and an upper copper layer.
8. The method according to claim 7 , wherein the upper copper layer is thicker than the lower molybdenum layer.
9. A method for fabricating an array substrate for a liquid crystal display device, comprising:
forming a gate electrode and a gate line on a substrate;
forming a semiconductor layer on the gate electrode and the gate line;
forming source and drain electrodes on the semiconductor layer and a data line crossing the gate line, wherein at least one of the gate line and the data line is a multiple layer including at least one of copper layer and molybdenum layer; and
etching the multiple layer with an etching solution, wherein an etching solution includes: hydrogen peroxide to etch the copper layer; fluoric compound to etch the molybdenum layer; organic acid to control a pH value of the etching solution; a first additive to control an etching speed; and a phosphate to control a taper angle of the multiple layer.
10. The method according to claim 9 , wherein the multiple layer includes molybdenum (Mo) layer and copper (Cu) layer.
11. The method according to claim 9 , wherein the multiple layer includes a bottom molybdenum (Mo) layer, a middle copper (Cu) layer, and a top molybdenum (Mo) layer.
12. The method according to claim 9 , wherein the multiple layer includes a plurality of molybdenum (Mo) layers and a plurality of copper (Cu) layers.
13. The method according to claim 10 , wherein the copper (Cu) layer is thicker than the molybdenum (Mo) layer.
14. The method according to claim 9 , wherein a taper angle of the multiple layer is in a range of about 30 degrees to about 60 degrees.
15. The method according to claim 9 , further comprising forming a storage electrode overlapping with the gate line to form a storage capacitor.