IP Library › Granted Patent US 7,795,092
Granted Patent B2
US 7,795,092 · App. 12/132,450 · Granted Sep 14, 2010

Semiconductor device and manufacturing method thereof

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,795,092
App. No.
12/132,450
Granted
Sep 14, 2010
Kind
B2
Abstract

A semiconductor memory device includes gate electrodes extending in a first direction above a surface of a substrate. The semiconductor memory device also includes a reinforcement insulation film formed in a line shape and extending in a second direction crossing the gate electrodes in a plane view viewed from above the surface of the substrate, and connected to adjacent gate electrodes. Further, the semiconductor memory device includes an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.

Claims (9)

1. A method of manufacturing a semiconductor memory device, comprising:

forming a first gate dielectric film on a semiconductor substrate, a floating gate on the first gate dielectric film, a second gate dielectric film on the floating gate, and a control gate on the second gate dielectric film, the first gate dielectric film, the floating gate, the second gate dielectric film, and the control gate being formed in a stripe shape;

depositing a first interlayer dielectric film between adjacent floating gates and between adjacent control gates;

depositing a reinforcement insulation film on an upper surface of the control gate, and on an upper surface of the first interlayer dielectric film, respectively;

processing in a stripe shape the reinforcement insulation film so as to extend to a direction crossing an extension direction of the control gate;

removing the first interlayer dielectric film through a gap of a stripe of the reinforcement insulation film; and

depositing a second interlayer dielectric film having poorer covering properties than that of the first interlayer dielectric film to block a region between an upper part of the adjacent control gates and an upper part of the gap of the stripe of the reinforcement insulation films before a region between the floating gates and a region beneath the reinforcement insulation film are filled.

2. The method of manufacturing a semiconductor memory according to claim 1 , wherein the reinforcement insulation film is formed by a silicon nitride film.

3. The method of manufacturing a semiconductor memory according to claim 1 , wherein the semiconductor memory device is a NAND type memory.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2008
From: MATSUOKA, YASUYUKI; KITO, MASARU; AOCHI, HIDEAKI; OKAMURA, TAKAYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 021445/0919 →
Priority Claims (1)
JP 2007-168671 · Jun 27, 2007 · national
Continuity (1)
Related Publication 20090001444A1 · Jan 1, 2009