Microelectronic assemblies with improved isolation voltage performance
Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
1. A microelectronic assembly comprising:
a semiconductor substrate having a first dopant type at a first concentration;
first and second buried layers having a second dopant type formed within the semiconductor substrate with a gap between the first and second buried layers, the first and second buried layers having a first end adjacent to the gap and a second end opposing the gap;
a barrier region formed within the gap and adjacent to the first ends of the first and second buried layers, the barrier region having the first dopant type at a second concentration, the second concentration being higher than the first concentration;
an epitaxial layer over the semiconductor substrate having the first dopant type at a third concentration, the third concentration being less than the second concentration;
first and second semiconductor devices over the epitaxial layer above the respective first and second buried layers, the first ends of the first and second buried layers extending a first depth from the first and second semiconductor devices and at least a portion of the barrier region extending a second depth from the first and second semiconductor devices, the second depth being greater than or equal to the first depth;
first and second well regions having the second dopant type within the epitaxial layer respectively above the first ends of the first and second buried layers; and
a barrier well having the first dopant type at a fourth concentration between the first and second well regions, the fourth concentration being greater than the first concentration.
2. The microelectronic assembly of claim 1 , wherein the barrier well is adjacent to the first and second well regions and the barrier region and the first and second well regions are adjacent to the respective first and second buried layers and are arranged such that the gap between the first and second buried layers further extends between the first and second well regions.
3. The microelectronic assembly of claim 2 , wherein the gap has a first width at the first ends of the first and second buried layers and a second width at the first sides of the first and second well regions, the first width being substantially equal to the second width.
4. The microelectronic assembly of claim 3 , wherein the gap has a first width at the first ends of the first and second buried layers and a second width at the first sides of the first and second well regions, the first width being greater than the second width.
5. The microelectronic assembly of claim 4 , wherein the first and second well regions are annularly shaped and are over the second ends of the first and second buried layers.
6. The microelectronic assembly of claim 4 , further comprising a shallow trench isolation (STI) region between the first and second semiconductor devices and above the first and second well regions and the barrier well.
7. A microelectronic assembly comprising:
first and second semiconductor devices formed over a substrate having a first dopant type at a first concentration;
first and second buried regions having a second dopant type respectively below the first and second semiconductor devices with a gap between the first and second buried regions, the first and second buried regions each having first ends adjacent to the gap and second ends opposing the gap, the first ends extending a first depth from the first and second semiconductor devices;
an epitaxial layer having the first dopant type over the substrate;
at least one well region over the substrate and between the first and second semiconductor devices; and
a barrier region having the first dopant type at a second concentration between and adjacent to the first ends of the first and second buried regions such that at least a portion of the barrier region extends a second depth from the first and second semiconductor devices, the second concentration being greater than the first concentration and the second depth being greater than or equal to the first depth.
8. The microelectronic assembly of claim 7 , wherein the at least one well region comprises first and second well regions having the second dopant type respectively above and adjacent to the first and second buried regions and arranged such that the gap between the first and second buried regions further extends between the first and second well regions.
9. The microelectronic assembly of claim 8 , further comprising a barrier well having the first dopant type at a third concentration between the first and second well regions, the third concentration being greater than the first concentration.
10. The microelectronic assembly of claim 8 , wherein the first and second well regions each have a first side adjacent to the gap and a second side opposing the gap.
11. The microelectronic assembly of claim 10 , wherein the gap has a first width at the first ends of the first and second buried regions and a second width at the first sides of the first and second well regions, the first width being substantially equal to the second width.
12. The microelectronic assembly of claim 10 , wherein the gap has a first width at the first ends of the first and second buried regions and a second width at the first sides of the first and second well regions, the first width being greater than the second width.
13. A microelectronic assembly comprising:
first and second buried layers formed in a semiconductor substrate having a first dopant type at a first concentration with a gap between the first and second buried layers, the first and second buried layers having a second dopant type and each having a first end adjacent to the gap and a second end opposing the gap;
a barrier region within the gap and adjacent to the first ends of the first and second buried layers, the barrier region having the first dopant type at a second concentration, the second concentration being higher than the first concentration;
an epitaxial layer having the first dopant type over the semiconductor substrate;
first and second semiconductor devices over the epitaxial layer above the respective first and second buried layers; and
first and second well regions having the second dopant type within the epitaxial layer respectively above the first ends of the first and second buried layers.
14. The microelectronic assembly of claim 13 , wherein the first ends of the first and second buried layers extend a first depth from the first and second semiconductor devices and at least a portion of the barrier region extends a second depth from the first and second semiconductor devices, the second depth being greater than or equal to the first depth.
15. The microelectronic assembly of claim 14 , wherein the first and second well regions are adjacent to the respective first and second buried layers and are arranged such that the gap between the first and second buried layers further extends between the first and second well regions.
16. The microelectronic assembly of claim 15 , further comprising a barrier well having the first dopant type at a third concentration between the first and second well regions, the third concentration being greater than the first concentration.
17. The microelectronic assembly of claim 16 , further comprising a shallow trench isolation (STI) region between the first and second semiconductor devices and above the first and second well regions and the barrier well.
18. The microelectronic assembly of claim 13 , wherein the gap has a first width at the first ends of the first and second buried layers and a second width at first sides of the first and second well regions, the first width being substantially equal to the second width.
19. The microelectronic assembly of claim 13 , wherein the gap has a first width at the first ends of the first and second buried layers and a second width at first sides of the first and second well regions, the first width being greater than the second width.
20. The microelectronic assembly of claim 13 , wherein the first and second well regions are annularly shaped and are over the second ends of the first and second buried layers.