Balanced amplifier with protection circuit
According to an exemplary embodiment, a balanced amplifier includes an in-phase amplifier coupled to a first input port of an output coupler and a quadrature amplifier coupled to a second input port of the output coupler. The balanced amplifier further includes an impedance termination coupled to an isolated port of the output coupler. The balanced amplifier further includes a protection circuit coupled to the isolated port of the output coupler and configured to limit an amount of power applied across the impedance termination. The balanced amplifier further includes an input coupler having a first output port coupled to an input of the in-phase amplifier and a second output port coupled to an input of the quadrature amplifier.
1. A balanced amplifier comprising:
an in-phase amplifier coupled to a first input port of an output coupler and a quadrature amplifier coupled to a second input port of said output coupler;
an impedance termination coupled to an isolated port of said output coupler;
a protection circuit comprising a voltage clamp coupled to said isolated port of said output coupler and configured to limit an amount of power applied across said impedance termination, the voltage clamp comprising a group of one or more electronic devices having a threshold voltage, wherein when a voltage at said isolated port of said output coupler exceeds the threshold voltage the group of one or more electronic devices shunts a current through the devices to ground.
2. The balanced amplifier of claim 1 further comprising an input coupler having a first output port coupled to an input of said in-phase amplifier and a second output port coupled to an input of said quadrature amplifier.
3. The balanced amplifier of claim 1 , wherein said voltage clamp comprises a first group of series-coupled diodes coupled in parallel with a second group of series-coupled diodes.
4. The balanced amplifier of claim 1 , wherein said voltage clamp comprises a first group of series-coupled FETs coupled in parallel with a second group of series-coupled FETs, wherein each of said series-coupled FETs in said first and second groups have a gate shorted to a drain.
5. The balanced amplifier of claim 2 , wherein said input and said output couplers each comprise a quadrature coupler.
6. The balanced amplifier of claim 5 , wherein each of said input and said output couplers is a quadrature coupler selected from the group consisting of a branchline quadrature coupler and a Lange quadrature coupler.
7. The balanced amplifier of claim 4 , wherein each of said series-coupled FETs in said first and second groups comprise an NFET.
8. The balanced amplifier of claim 1 , wherein an output port of said output coupler provides an RF output signal of said balanced amplifier.
9. The balanced amplifier of claim 2 , wherein said input coupler has an input port for receiving an RF input signal of said balanced amplifier.
10. A semiconductor die comprising a balanced amplifier, said balanced amplifier comprising:
an in-phase amplifier coupled to a first input port of an output coupler and a quadrature amplifier coupled to a second input port of said output coupler;
an impedance termination coupled to an isolated port of said output coupler;
a protection circuit comprising a voltage clamp coupled to said isolated port of said output coupler and configured to limit an amount of power applied across said impedance termination, the voltage clamp comprising a group of one or more electronic devices having a threshold voltage, wherein when a voltage at said isolated port of said output coupler exceeds the threshold voltage the group of one or more electronic devices shunts a current through the devices to ground.
11. The semiconductor die of claim 10 , wherein said balanced amplifier further comprises an input coupler having a first output port coupled to an input of said in-phase amplifier and a second output port coupled to an input of said quadrature amplifier.
12. The semiconductor die of claim 10 , wherein said voltage clamp comprises a first group of series-coupled diodes coupled in parallel with a second group of series-coupled diodes.
13. The semiconductor die of claim 10 , wherein said voltage clamp comprises a first group of series-coupled FETs coupled in parallel with a second group of series-coupled FETs, wherein each of said series-coupled FETs in said first and second groups have a gate shorted to a drain.
14. The semiconductor die of claim 11 , wherein said input and said output couplers each comprise a quadrature coupler.
15. The semiconductor die of claim 14 , wherein each of said input and output couplers is a quadrature coupler selected from the group consisting of a branchline quadrature coupler and a Lange quadrature coupler.
16. The semiconductor die of claim 10 , wherein an output port of said output coupler provides an RF output signal of said balanced amplifier.
17. The semiconductor die of claim 11 , wherein said input coupler has an input port for receiving an RF input signal for said balanced amplifier.
18. The semiconductor die of claim 10 , wherein said semiconductor die is utilized in an electronic system selected from the group consisting of a wired or wireless communications device, a cell phone, a switching device, a router, a repeater, a codec, a wired or wireless LAN, a WLAN, a Bluetooth enabled device, a satellite set top box, a cable modem, a printer, a copier, an RF transceiver, and a personal digital assistant (PDA).