Semiconductor device

1. A semiconductor device comprising:

a well region in a substrate;

a transistor, configured on a the substrate;

a strain auxiliary layer, disposed on the substrate and above the well region at a periphery of the transistor besides and directly connecting source/drain regions of the transistor, wherein the strain auxiliary layer has a top surface lower than a top surface of a contact directly connected to the source/drain regions of the transistor; and

a strain layer, disposed on the same substrate and above the same well region, covering the transistor and the well region at a center of the transistor not covered by the strain auxiliary layer, wherein a stress provided by the strain layer is different from a stress provided by the strain auxiliary layer.

2. The semiconductor device according to claim 1 , wherein the strain auxiliary comprises two sections, correspondingly disposed on the substrate at the periphery of the transistor.

3. The semiconductor device according to claim 2 , wherein the two sections of the strain auxiliary layer are configured above a part of an isolation region.

4. The semiconductor device according to claim 3 , wherein the two sections of the strain auxiliary layer are respectively configured in proximity to two source/drain regions of the transistor.

5. The semiconductor device according to claim 4 , wherein the two sections of the strain auxiliary layer are correspondingly respectively delineated at one side of each source/drain region of the transistor, wherein the one side of each source/drain region is substantially parallel to an extension direction of a gate of the transistor.

6. The semiconductor device according to claim 2 , wherein one of the two sections of the strain auxiliary layer covers a part of a common source/drain region of the transistor and another one of the two sections of the strain auxiliary layer is disposed over a part of an isolation structure in the substrate.

7. The semiconductor device according to claim 6 , wherein the other one of the two sections of the strain auxiliary layer is delineated extending along one side of a source/drain region of the transistor, wherein the one side of the source/drain region is substantially parallel to an extension direction of a gate of the transistor.

8. The semiconductor device according to claim 2 , wherein the strain auxiliary layer having a ring-like configuration that encircles a periphery of the transistor, the ring-like configuration of the auxiliary layer comprising:

the two sections; and

two connecting parts to connect the two sections.

9. The semiconductor device according to claim 8 , wherein the two sections of the ring-like configuration extend along one side of a source/drain region of the transistor, wherein the one side of the source/drain region is substantially parallel to an extension direction of a gate of the transistor.

10. The semiconductor device according to claim 1 , wherein the strain layer and the strain auxiliary layer provide opposite types of stress.

11. The semiconductor device according to claim 10 , wherein the transistor is an N-type channel metal oxide semiconductor transistor, and the strain auxiliary layer is a tensile film layer, while the strain layer is a compressive film layer.

12. The semiconductor device according to claim 10 , wherein the transistor is a P-type channel metal oxide semiconductor transistor, and the strain auxiliary layer is a compressive film layer, while the strain layer is a tensile film layer.

13. A semiconductor device, comprising:

a substrate, comprising a first conductive type well region and a second conductive type well region;

a first conductive type metal oxide semiconductor transistor, configured on the substrate within the boundary of the second conductive type well region;

a second conductive type metal oxide semiconductor transistor, configured on the substrate within the boundary the first conductive type well region;

a first strain layer, disposed on the substrate and above a part of the first conductive type well region at a center of the first conductive type metal oxide semiconductor transistor and a part of the second conductive type well region at a periphery of the second conductive channel metal oxide semiconductor transistor, wherein the periphery of the second conductive channel metal oxide semiconductor transistor besides and directly connected to source/drain regions of the second conductive channel metal oxide semiconductor transistor; and

a second strain layer, disposed on the substrate and above another part of the first conductive well region at a periphery of the first conductive type metal oxide semiconductor transistor not covered by the first strain layer and another part of the second conductive well region at a center of the second conductive channel metal oxide semiconductor transistor not covered by the first strain layer, wherein the periphery of the first conductive channel metal oxide semiconductor transistor besides and directly connecting source/drain regions of the first conductive channel metal oxide semiconductor transistor, and

wherein a stress provided by the second strain layer is different from a stress provided by the first strain layer, and a top surface of the first strain layer and a top surface of the second strain layer are lower a top surface of a contact directly connected to one of source/drain regions of the first conductive channel metal oxide semiconductor transistor or the second conductive channel metal oxide semiconductor transistor.

14. The semiconductor device of claim 13 , wherein the stress provided by the second strain layer is opposite to the stress provided by the first strain layer.

15. The semiconductor device of claim 14 , wherein the first conductive type includes an N-type, while the second conductive type includes a P-type.

16. The semiconductor device of claim 14 , wherein the first strain layer includes a tensile film layer, while the second strain layer includes compressive film layer.

17. The semiconductor device of claim 13 , wherein the first strain layer configured on part of the first conductive type well region includes two sections, correspondingly disposed on the substrate.

18. The semiconductor device of claim 17 , wherein the two sections of the first strain layer are disposed on the part of the isolation region in the substrate.

19. The semiconductor device of claim 18 , wherein the two sections of the first strain layer are configured respectively in proximity to two source/drain regions of the first conductive type channel metal oxide semiconductor transistor.

20. The semiconductor device of claim 19 , wherein the two sections of the first strain layer are correspondingly respectively disposed at one side of each source/drain regions of the first conductive type channel metal oxide semiconductor transistor, wherein the one side of each source/drain regions is substantially parallel to an extension direction of a gate of the first conductive type channel metal oxide semiconductor transistor.

21. The semiconductor device of claim 17 , wherein one of the two sections of the first strain layer covers a part of a common source/drain region of the first conductive type channel metal oxide transistor, and another one of the two sections of the first strain layer is configured on the part of the isolation region in the substrate.

22. The semiconductor device of claim 17 , wherein the first strain layer disposed on the second conductive type well region has a ring-like configuration encircling a periphery of the transistor, wherein the ring-like configuration comprises:

the two sections; and

two connecting parts to connect the two sections.

23. The semiconductor device of claim 13 , wherein the second strain layer on the other part of the first conductive type well region comprises two sections correspondingly disposed on the substrate.

24. The semiconductor device of claim 23 , wherein the two sections of the second strain layer are respectively disposed on the part of the isolation region of the substrate.

25. The semiconductor device of claim 24 , wherein the two sections of the second strain layer are respectively disposed in proximity to two source/drain regions of the second conductive type channel metal oxide semiconductor transistor.

26. The semiconductor device of claim 25 , wherein the two sections of the second strain layer correspondingly respectively dispose at one side of each source/drain regions of the second conductive type channel metal oxide semiconductor transistor, wherein the one side of each source/drain regions is substantially parallel to an extension direction of a gate of the second conductive type channel metal oxide semiconductor transistor.

27. The semiconductor device of claim 23 , wherein one of the two sections of the second strain layer covers a part of one common source/drain region of the second conductive type channel metal oxide transistor, and another one of the two sections of the second strain layer is configured on the part of a isolation region in the substrate.

28. The semiconductor device of claim 23 , wherein the second strain layer disposed on the first conductive type well region has a ring-like configuration encircling a periphery of the second conductive type channel metal oxide transistor, wherein the ring-like configuration comprises:

the two sections; and

two connecting parts to connect the two sections.