Semiconductor device and method of forming the same
A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.
1. A semiconductor device comprising:
a first well region;
a second well region;
a well isolation region disposed between the first well region and the second well region, the well isolation region isolating the first well region and the second well region from each other;
the first and second well regions each including an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove;
the first well region including a first well layer;
the second well region including a second well layer;
the well isolation region including a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove; and
the first and second well layers having first and second bottoms respectively, and the first and second bottoms being deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.
2. The semiconductor device according to claim 1 , wherein the diffusion stopper layer includes a semiconductor layer that contains at least one of carbon, nitrogen, fluorine, and germanium.
3. The semiconductor device according to claim 1 , wherein the well isolation groove has a width that is substantially similar to the width of the well isolation region defined between the first and second well regions.
4. The semiconductor device according to claim 1 , wherein the well isolation groove has a width that is narrower than the width of the well isolation region defined between the first and second well regions.
5. The semiconductor device according to claim 1 , wherein the first and second well layers and the diffusion stopper layer are disposed in a silicon substrate.
6. The semiconductor device according to claim 1 , wherein the first well layer has a first conductivity type, and the second well layer has a second conductivity type different from the first conductivity type.