Selective deposition of amorphous silicon films on metal gates

1. A process comprising:

forming an amorphous silicon film upon a substrate, the substrate including: a gate electrode disposed above a semiconductive body, including a gate electrode upper surface and at lease one sidewall;

a nitride etch stop layer (NESL) disposed above and on the semiconductive body;

a spacer disposed on the at least one sidewall; and

an interlayer dielectric (ILD) first layer including an ILD first layer upper surface, wherein the gate electrode upper surface and the ILD first layer upper surface are substantially coplanar, wherein forming the amorphous silicon film is carried out under conditions to accumulate on the metal gate upper surface and not on the ILD first layer upper surface; and

forming an etch stop layer from the amorphous silicon film.

2. The process of claim 1 , wherein accumulation of the amorphous silicon film is achieved by selectively etching back the amorphous silicon film to remove amorphous silicon disposed upon the ILD first layer upper.

3. The process of claim 1 , further including:

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; and

etching a gate electrode partial via through the ILD cap layer that stops on the etch stop layer.

4. The process of claim 1 , further including:

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; and

simultaneously etching a gate electrode complete via through the ILD cap layer that stops on the amorphous silicon film.

5. The process of claim 1 , further including converting the amorphous silicon to a dielectric material under nitriding conditions to achieve silicon nitride.

6. The process of claim 1 , further including converting the amorphous silicon to a dielectric material under oxidizing conditions to achieve silicon oxide.

7. The process of claim 1 , further including converting the amorphous silicon to a dielectric material under carburizing conditions to achieve silicon carbide.

8. The process of claim 1 , further including converting the amorphous silicon to a dielectric material under conditions to achieve silicon oxynitride.

9. The process of claim 1 , further including:

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; followed by

etching a gate electrode complete via through the ILD cap layer that stops on the gate electrode.

10. The process of claim 1 , further including:

forming an ILD cap layer over the ILD first layer;

etching a gate electrode complete via through the ILD cap layer that stops on the gate electrode; followed by

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL.

11. The process of claim 1 , wherein forming the amorphous silicon film upon the substrate includes getting the amorphous silicon to accumulate on the metal gate upper surface and not on the ILD first layer upper surface.

12. A process comprising:

forming an amorphous silicon film upon a substrate,

the substrate including:

a gate electrode disposed above a semiconductive body, including a gate electrode upper surface and at lease one sidewall;

a nitride etch stop layer (NESL) disposed above and on the semiconductive body;

a spacer disposed on the at least one sidewall; and

an interlayer dielectric (ILD) first layer including an ILD first layer upper surface, wherein the gate electrode upper surface and the ILD first layer upper surface are substantially coplanar,

wherein forming the amorphous silicon film is carried out under conditions of getting the amorphous silicon to accumulate on the metal gate upper surface and not on the ILD first layer upper surface.

13. The process of claim 12 , wherein getting the amorphous silicon to accumulate on the metal gate upper surface and not on the ILD first layer upper surface includes:

depositing using at least one of silane (SiH 4 ) and disilane (Si2H6) at a temperature between 250-400 degrees Celsius, at a pressure of 0.1-10 Torr, for a time duration of 1-30 seconds, and with RF power of 10-3,000 Watt.

14. The process of claim 12 , wherein the spacer is an inner spacer adjacent the gate electrode, the substrate further including an outer spacer adjacent the inner spacer, the process further including:

forming an etch stop layer from the amorphous silicon film.

15. The process of claim 12 , wherein getting the amorphous silicon to accumulate on the metal gate upper surface and not on the ILD first layer upper surface includes:

depositing using at least one of silane (SiH 4 ) and disilane (Si2H6) at a temperature between 250-400 degrees Celsius, at a pressure of 0.1-10 Torr, for a time duration of 1-30 seconds, and with RF power of 10-3,000 Watt, and the process further including:

forming an etch stop layer from the amorphous silicon film.

16. The process of claim 12 , further including:

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; and

etching a gate electrode partial via through the ILD cap layer that stops on the etch stop layer.

17. The process of claim 12 , further including:

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; and

simultaneously etching a gate electrode complete via through the ILD cap layer that stops on the amorphous silicon film.

18. The process of claim 12 , further including converting the amorphous silicon to a dielectric material under nitriding conditions to achieve silicon nitride.

19. The process of claim 12 , further including converting the amorphous silicon to a dielectric material under oxidizing conditions to achieve silicon oxide.

20. The process of claim 12 , further including converting the amorphous silicon to a dielectric material under carburizing conditions to achieve silicon carbide.

21. The process of claim 12 , further including converting the amorphous silicon to a dielectric material under conditions to achieve silicon oxynitride.

22. The process of claim 12 , further including:

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; followed by

etching a gate electrode complete via through the ILD cap layer that stops on the gate electrode.

23. A process comprising:

forming an amorphous silicon film upon a substrate,

the substrate including:

a gate electrode disposed above a semiconductive body, including a gate electrode upper surface and at lease one sidewall;

a nitride etch stop layer (NESL) disposed above and on the semiconductive body;

a spacer disposed on the at least one sidewall; and

an interlayer dielectric (ILD) first layer including an ILD first layer upper surface, wherein the gate electrode upper surface and the ILD first layer upper surface are substantially coplanar,

wherein forming the amorphous silicon film is carried out under conditions of getting the amorphous silicon to accumulate on the metal gate upper surface and not on the ILD first layer upper surface, the conditions including:

depositing using at least one of silane (SiH 4 ) and disilane (Si2H6) at a temperature between 250-400 degrees Celsius, at a pressure of 0.1-10 Torr, for a time duration of 1-30 seconds, and with RF power of 10-3,000 Watt;

forming an etch stop layer from the amorphous silicon film;

forming an ILD cap layer over the ILD first layer;

etching source- and drain contact vias through the ILD cap layer, the ILD first layer, and the NESL; and

etching a gate electrode via through the ILD cap layer that stops on the etch stop layer.

24. The process of claim 23 , wherein etching a gate electrode via includes etching a partial via that stops on the etch stop layer that was formed from the amorphous silicon layer.

25. The process of claim 23 , wherein etching a gate electrode via includes etching and stopping on the gate electrode while simultaneously etching source- and drain vias.