Method of controlling stress in gallium nitride films deposited on substrates
View Patent ↗Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
1. A semiconductor structure, comprising:
a silicon substrate; and
a single crystal group-III nitride graded layer on the silicon substrate, wherein at room temperature the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress.
2. The semiconductor structure of claim 1 , further comprising a device layer on a side of the single crystal group-III nitride graded layer opposite to the silicon substrate.
3. The semiconductor structure of claim 2 , wherein the device layer includes a group-III nitride material and aluminum.
4. The semiconductor structure of claim 3 , wherein the device layer is formed of GaN at a portion of the device layer that is distal from the single crystal group-III graded nitride layer.
5. The semiconductor structure of claim 2 , further comprising a source, drain and gate.
6. The semiconductor structure of claim 2 , wherein a transistor is formed in the device layer.
7. The semiconductor structure of claim 2 , wherein a diode is formed in the device layer.
8. The semiconductor structure of claim 2 , wherein the device layer has a thickness exceeding 5 microns.
9. The semiconductor structure of claim 1 , wherein the continuous grade varies linearly.
10. The semiconductor structure of claim 1 , wherein the continuous grade varies at a greater rate at a region proximate to the silicon substrate than distal from the substrate.
11. The semiconductor structure of claim 1 , wherein the continuous grade varies at a slower rate at a region proximate to the silicon substrate than distal from the substrate.
12. The semiconductor structure of claim 1 , wherein:
a surface of the group-III nitride graded layer has a dislocation density that is higher in a portion of the graded layer that is proximate to the silicon substrate than in a portion of the graded layer that is distal from the silicon substrate; and
the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
13. The semiconductor structure of claim 1 , wherein:
a surface of the group-III nitride graded layer has a dislocation density that is between 10 9 -10 10 cm −2 ; and
the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
14. The semiconductor structure of claim 1 , wherein:
the graded layer has a total thickness of about 1 micron; and
the structure further comprises layer of GaN on an opposite side of the graded gallium nitride layer from the silicon substrate.
15. The semiconductor structure of claim 1 , wherein:
the graded layer has a total thickness of about 1 micron;
a portion of the layer closest to the silicon substrate is AlGaN and a portion of the layer furthest from the silicon substrate has less aluminum than the portion closest to the silicon substrate; and
the grade is limited to between 20 to 80% of the thickness of the layer.
16. The semiconductor structure of claim 1 , wherein the graded layer is free of cracks.
17. A semiconductor structure, comprising:
a silicon substrate;
a single crystal group-III nitride graded layer on the silicon substrate, wherein the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress; and
a group-III nitride device layer on a side of the graded layer opposite to the silicon substrate.
18. The semiconductor structure of claim 17 , wherein the device layer includes at least a portion that is GaN.
19. The semiconductor structure of claim 17 , wherein:
the graded layer is free of cracks; and
the device layer includes a plurality of layers and a transistor is formed in the plurality of layers.
20. The semiconductor structure of claim 17 , wherein:
the graded layer is free of cracks; and
the device layer includes a plurality of layers and a diode is formed in the plurality of layers.