HDMI controller circuit for transmitting digital data to compatible audio device using address decoder where values are written to registers of sub-circuits
The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the sub-circuits are configured by using the circuit interface, address decoder, and bus to write values to the registers of the sub-circuits. The sub-circuits of the controller include a video pixel sampler, an audio sampler, a frame composer, and a power controller. The video sampler can be configured to convert one of a plurality of RGB and YCbCr signals to a common format signal used by other sub-circuits of the controller.
1. A High-Definition Multimedia Interface (HDMI) controller circuit, comprising:
a circuit interface;
an address decoder coupled to the circuit interface;
a plurality of sub-circuits, each having a plurality of registers used to configure and control the associated sub-circuit; and
a bus that couples the plurality of registers of each sub-circuit to the address decoder,
wherein the circuit interface, address decoder, and bus are configured to write values to the registers of the sub-circuits to configure the sub-circuits upon powering-up the controller circuit.
2. The controller circuit of claim 1 , wherein the plurality of sub-circuits include an audio sampler configured to sample an input audio signal and store the samples in a buffer.
3. The controller circuit of claim 2 , wherein the audio sampler is configured to sample one of an Inter-IC Sound (I 2 S) format audio signal and a Sony/Philips Digital Interconnect Format (S/PDIF) audio signal.
4. The controller circuit of claim 1 , wherein the plurality of sub-circuits include a video pixel sampler configured to convert an input video signal to a common format signal used by another sub-circuit of the electronic circuit.
5. The controller circuit of claim 4 , wherein the video sampler is configured to convert one of a plurality of RGB and YCbCr signals to the common format signal.
6. The controller circuit of claim 1 , wherein the plurality of sub-circuits includes a frame composer having a data island scheduler.
7. The controller circuit of claim 6 , wherein the data island scheduler is a round-robin state machine configured to schedule packet insertion in an input video frame.
8. The controller circuit of claim 6 , wherein the data island scheduler is configured to schedule packets by inserting packet descriptors into one of a low priority packet queue and a high priority packet queue.
9. The controller circuit of claim 6 , wherein the data island scheduler is configurable to schedule a packet to be inserted at a selected input video frame rate.
10. The controller circuit of claim 6 , wherein the data island scheduler is configurable to schedule a packet to be inserted at a selected input video line rate.
11. The controller circuit of claim 1 , wherein the plurality of sub-circuits includes a power controller that manages the power consumption of the electronic circuit.
12. The controller circuit of claim 11 , wherein the power controller is configured to implement a power down mode, a standby mode, a feed through mode, and a high-bandwidth digital-content protection (HDCP) power down mode.
13. A tangible computer readable storage medium that includes a High-Definition Multimedia Interface (HDMI) controller circuit embodied in software, the controller circuit comprising:
a circuit interface;
an address decoder coupled to the circuit interface;
a plurality of sub-circuits, each having a plurality of registers used to configure and control the associated sub-circuit; and
a bus that couples the plurality of register of each sub-circuit to the address decoder,
wherein the circuit interface, address decoder, and bus are configured to write values to the registers of the sub-circuits to configure the sub-circuits upon powering-up the controller circuit.
14. The tangible computer readable storage medium of claim 13 , wherein the plurality of sub-circuits include an audio sampler configured to sample an input audio signal and store the samples in a buffer.
15. The tangible computer readable storage medium of claim 13 , wherein the plurality of sub-circuits include a video pixel sampler configured to convert an input video signal to a common format signal used by other sub-circuit of the electronic circuit.
16. The tangible computer readable storage medium of claim 13 , wherein the plurality of sub-circuits includes a frame composer having a data island scheduler.
17. The tangible computer readable storage medium of claim 13 , wherein the processor is embodied in hardware description language software.
18. The tangible computer readable storage medium of claim 13 , wherein the processor is embodied in one of Verilog hardware description language software and VHDL hardware description language software.