System and method for asynchronous clock regeneration

1. A method of asynchronous clock regeneration, comprising:

synchronizing a first write pointer and a second write pointer, including allowing the first write pointer to sample data from the second write pointer for synchronizing the write pointers, the first write pointer being communicatively coupled with the second write pointer, the first write pointer being an offline write pointer of an offline FIFO connected to an offline data path for voltage and temperature compensation, the second write pointer being an online write pointer of an online FIFO connected to an online data path;

swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static; and

regenerating a DQS (Data Strobe Signal) clock from a signal received from the swapped write pointers within the system clock domain, including creating a falling edge of the regenerated DQS (Data Strobe Signal) clock and, when burst DQS (Data Strobe Signal) clocking, generates a pulse during asynchronous reset, removing the pulse and holding the regenerated DQS clock in a low state to suppress additional pulses,

wherein the sampled data is sampled directly from within a DQS domain.

2. A method as claimed in claim 1 , wherein swapping occurs in a sequence determined in a system clock domain.

3. A method as claimed in claim 1 , wherein the step of synchronizing the first write pointer and the second write pointer further includes:

utilizing sampled data for determining when the bits are static.

4. A method as claimed in claim 1 , further comprising:

bypassing FIFOs (First-In First-Out Data Buffers) via regeneration of the DQS (Data Strobe Signal) clock, thereby preserving minimum read path latency.

5. A computer-readable medium having computer-executable instructions for performing a method of asynchronous clock regeneration, said method comprising:

synchronizing a first write pointer and a second write pointer, including allowing the first write pointer to sample data from the second write pointer for synchronizing the write pointers, the first write pointer being communicatively coupled with the second write pointer, the first write pointer being an offline write pointer of an offline FIFO connected to an offline data path for voltage and temperature compensation, the second write pointer being an online write pointer of an online FIFO connected to an online data path;

swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static; and

regenerating a DQS (Data Strobe Signal) clock from a signal received from the swapped write pointers within the system clock domain, including creating a falling edge of the regenerated DQS (Data Strobe Signal) clock and, when burst DQS (Data Strobe Signal) clocking generates a pulse during asynchronous reset, removing the pulse and holding the regenerated DQS clock in a low state to suppress additional pulses,

wherein the sampled data is sampled directly from within a DQS domain.

6. A computer-readable medium as claimed in claim 5 , wherein swapping occurs in a sequence determined in a system clock domain.

7. A computer-readable medium as claimed in claim 5 , wherein the step of synchronizing the first write pointer and the second write pointer further includes:

utilizing sampled data for determining when the bits are static.

8. A computer-readable medium as claimed in claim 5 , further comprising:

bypassing FIFOs (First-In First-Out Data Buffers) via regeneration of the DQS (Data Strobe Signal) clock, thereby preserving minimum read path latency.

9. A system for asynchronous clock regeneration, comprising:

a first write pointer and a second writer pointer, wherein the first write pointer samples data from the second write pointer for synchronizing the write pointers, the sampled data being sampled directly from within a DQS domain, the first write pointer being an offline write pointer of an offline FIFO connected to an offline data path for voltage and temperature compensation, the second write pointer being an online write pointer of an online FIFO connected to an online data path, the first write pointer and the second write pointer configured for being communicatively coupled with each other; and

a clock regeneration path communicatively coupled with the first and second write pointers, the clock regeneration path configured for regenerating a DQS (Data Strobe Signal) clock from a signal received from the swapped write pointers within the system clock domain, the clock regeneration path including a delay line, the delay line configured for creating a negative edge of the regenerated DQS (Data Strobe Signal) clock, the clock regeneration path further includes an AND logic gate, the AND logic gate being communicatively coupled with the delay line, the AND logic gate being configured for removing a pulse generated by burst DQS (Data Strobe Signal) clocking asynchronous reset, the system being configured for removing the pulse and holding the regenerated DQS clock in a low state to suppress additional pulses,

wherein the system allows for at least one bit of the first write pointer to be swapped with at least one bit of the second write pointer when the bits are static, thereby allowing for swapping without interrupting data flow under at least one of burst DQS (Data Strobe Signal) and continuous DQS (Data Strobe Signal) conditions.

10. A system as claimed in claim 9 , wherein swapping occurs in a sequence determined in a system clock domain.

11. A system as claimed in claim 9 , wherein the first write pointer is configured for sampling data from the second write pointer for determining if the bits are static.

12. A system as claimed in claim 10 , wherein swapping of the bits for regenerating the DQS (Data Strobe Signal) clock is accomplished from within the system clock domain.