Patterned backside stress engineering for transistor performance optimization

1. An apparatus comprising:

a first surface of a substrate haying a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader having a portion opposite the first transistor type region that is thinner than a portion opposite the second transistor type region, wherein the portion opposite the first transistor type region is about 0.1 to 1.25 mm thick and the portion opposite the second transistor type region is about 1.25 to 2.75 mm thick.

2. An apparatus comprising:

a first surface of a substrate having a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader having a portion opposite the first transistor type region that is thinner than a portion opposite the second transistor type region, wherein the portion opposite the first transistor type region is about 0.25 to 1.1 mm thick and the portion opposite the second transistor type region is about 1.25 to 2.75mm thick.

3. An apparatus comprising:

a first surface of a substrate haying a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader haying a portion opposite the first transistor type re gion that is thinner than a portion opposite the second transistor type region, wherein the portion opposite the first transistor type region is about 0.5 to 1.0 mm thick and the portion opposite the second transistor type region is about 1.5 to 2.5 mm thick.

4. The apparatus of claim 3 , further comprising:

a thermal interface material between the substrate surface opposite the first surface and the heat spreader.

5. The apparatus of claim 4 , wherein the heat spreader includes copper and the thermal interface material includes gold-tin.