Semiconductor device having a plurality of stacked transistors and method of fabricating the same
A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.
1. A semiconductor device, comprising:
a lower insulating layer on a semiconductor substrate;
an upper channel body pattern on the lower insulating layer;
a source region and a drain region within the upper channel body pattern;
a non-metal transfer gate electrode on the upper channel body pattern between the source and drain regions;
an intermediate insulating layer covering the non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer;
a metal word line within the intermediate insulating layer and contacting at least an upper surface of the non-metal transfer gate electrode;
an insulating spacer covering a sidewall of the metal word line; and
a metal node plug within the intermediate insulating layer and the lower insulating layer and in contact with the source region of the upper channel body pattern,
wherein a combined width of the insulating spacer and the metal word line is greater than a width of the non-metal transfer gate electrode, and
wherein the metal word line contacts the upper surface and at least one sidewall of the non-metal transfer gate electrode.
2. The semiconductor device according to claim 1 , further comprising:
a bulk transistor in the semiconductor substrate; and
a lower thin film transistor within the lower insulating layer,
wherein the metal node plug contacts a drain region of the lower thin film transistor and a drain region of the bulk transistor.
3. The semiconductor device according to claim 1 , wherein the non-metal transfer gate electrode is a polysilicon layer.
4. The semiconductor device according to claim 1 , wherein the metal word line and the metal node plug are tungsten layers.
5. The semiconductor device according to claim 1 , wherein an upper surface of the metal word line is higher than an upper surface of the metal node plug.
6. The semiconductor device according to claim 1 , wherein an upper surface of the metal word line is lower than an upper surface of the metal node plug.
7. The semiconductor device according to claim 6 , wherein a combined width of the insulating spacer and the metal word line is about equal to a width of the non-metal transfer gate electrode, and the metal word line is aligned with the non-metal transfer gate electrode.
8. The semiconductor device according to claim 1 , further comprising:
a ground line, a power line, and a bit line on the intermediate insulating layer,
wherein the bit line is electrically connected to the drain region of the upper channel body pattern.
9. A semiconductor device, comprising:
a lower insulating layer on a semiconductor substrate;
an upper channel body pattern on the lower insulating layer;
a source region and a drain region within the upper channel body pattern;
a non-metal transfer gate electrode on the upper channel body pattern between the source and drain regions;
an intermediate insulating layer covering the non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer;
a metal word line within the intermediate insulating layer and contacting at least an upper surface of the non-metal transfer gate electrode;
an insulating spacer covering a sidewall of the metal word line; and
a metal node plug within the intermediate insulating layer and the lower insulating layer and in contact with the source region of the upper channel body pattern,
wherein a combined width of the insulating spacer and the metal word line is greater than a width of the non-metal transfer gate electrode.