IP Library Granted Patent US 7,830,900
Granted Patent B2
US 7,830,900 · App. 11/215,931 · Granted Nov 9, 2010

Method and apparatus for an adaptive de-jitter buffer

Assignee: QUALCOMM Incorporated
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Quick Facts
Patent No.
US 7,830,900
App. No.
11/215,931
Granted
Nov 9, 2010
Kind
B2
Abstract

Adaptive De-Jitter Buffer for Voice over IP (VoIP) for packet switch communications. The de-jitter buffer methods and apparatus presented avoid playback of underflows while balancing end-to-end delay. In one example, the de-jitter buffer is recalculated at the beginning of each talkspurt. In another example, talkspurt packets are compressed upon receipt of all remaining packets.

Claims (155)

1. An apparatus, comprising:

a memory storage unit configured to store packets of data; and

a first controller configured to compare a number of packets stored in the memory storage unit to a first time warp threshold for the memory storage unit, the first controller further adapted to generate a time warp indicator when the number of stored packets violates the first time warp threshold, wherein the first time warp threshold comprises a first percentage of a target delay length of packets stored in the memory storage unit.

2. The apparatus as in claim 1 , wherein the apparatus further comprises:

an input controller configured to receive packets and store packets in the memory storage unit; and

an output controller coupled to the first controller and configured to receive the time warping indicator from the first controller.

3. The apparatus as in claim 2 , further comprising:

means for time warping packets in response to the time warp indicator, wherein the output controller is adapted to provide the time warp indicator to the means for time warping packets.

4. The apparatus as in claim 1 , wherein the first controller is further configured to compare the number of packets stored in the memory storage unit to a second time warp threshold for the memory storage unit and to generate the time warp indicator when the number of stored packets exceeds the second time warp threshold.

5. The apparatus as in claim 1 , wherein the first controller is further configured to generate a first value for the time warp indicator for expansion of packets.

6. The apparatus as in claim 1 , wherein the first controller is further configured to generate a second value for the time warp indicator for compression of packets.

7. The apparatus as in claim 6 , wherein the second value is a second percentage of the target delay length.

8. The apparatus as in claim 1 , wherein the first controller is further configured to generate the first value if a next sequential packet is not received within a first time period after a previous sequential packet.

9. The apparatus as in claim 1 , wherein the first controller is further configured to average a status of the memory storage unit over a time window.

10. The apparatus as in claim 9 , wherein:

the first controller is further configured to compare the number of packets stored in the memory storage unit to a second time warp threshold for the memory storage unit and to generate the time warp indicator when the number of stored packets exceeds the second time warp threshold; and

the first controller is further configured to compare the filtered number of packets stored in the memory storage unit to the first and second time warp thresholds.

11. The apparatus as in claim 1 , wherein the first controller is further configured to filter the number of packets stored in the memory storage unit over a time window.

12. The apparatus as in claim 11 , wherein the first controller is further configured to determine a target de-jitter buffer delay length, and determine the time window as a function of the target de-jitter buffer delay length.

13. The apparatus as in claim 1 , wherein the first controller is further configured to determine the target de-jitter buffer delay length as a target number of packets to be stored in the memory storage unit.

14. The apparatus as in claim 1 , wherein first controller is further configured to generate the time warp indicator as an instruction to compress the packet, expand the packet, or process the packet without time warping.

15. The apparatus as in claim 1 , wherein the memory storage unit comprises an adaptive de-jitter buffer.

16. A processor-implemented method for processing packets of data, the method comprising:

storing packets of data in a memory storage unit;

comparing a number of packets stored in the memory storage unit to. a first time warp threshold, wherein the first time warp threshold comprises a first percentage of a target delay length of packets stored in the memory storage unit; and

generating a time warp indicator when the number of packets stored in the memory storage unit violates the first time warp threshold.

17. The method as in claim 16 , further comprising:

in response to the time warp indicator, time warping at least one packet.

18. The method as in claim 16 , further comprising:

comparing the number of packets stored in the memory storage unit to a second time warp threshold; and

generating a time warp indicator at a first value when the number of packets stored in the memory storage unit is less than the first time warp threshold and at a second value when the number of packets stored in the memory storage unit exceeds the second time warp threshold.

19. The method as in claim 16 , further comprising:

expanding at least one packet when the time warp indicator is the first value; and

compressing at least one packet when the time warp indicator is a second value.

20. The method as in claim 19 , further comprising:

receiving a plurality of sequential packets; and

add-overlapping segments of the sequential packets in response to the time warp indicator.

21. The method as in claim 20 , further wherein add-overlapping further comprises:

combining at least two of the plurality of segments as:

a

)

OutSegment

[

i

]

=

(

Segment1

(

i

)

*

(

WindowSize

-

i

)

+

(

Segment

2

(

i

)

*

i

)

WindowSize

b

)

OutSegment

[

i

]

=

(

Segment

2

(

i

)

*

(

WindowSize

-

i

)

+

(

Segment

1

(

i

)

*

i

)

WindowSize

i

=

0

WindowSize

-

1

WindowSize

=

RWindowSize

wherein OutSegment is a resultant add-overlapped segment;

Segment1 and Segment2 are the at least two of the plurality of segments to be add-overlapped;

WindowSize corresponds to a first segment; and

RWindowSize corresponds to a second segment.

22. The method of claim 16 , further comprising:

determining a first time warp threshold by tracking a number of delayed packets.

23. The method of claim 22 , wherein a delayed packet is a packet received after an associated anticipated playback time of the packet.

24. The method of claim 16 , further comprising:

time warping at least one packet; and

playing back the at least one time warped packet.

25. A computer-readable storage medium containing a set of instructions for execution by a processor, the set of instructions comprising:

an input routine for storing packets of data in a memory storage unit;

a first routine for comparing the number of packets stored in the memory storage unit to a second time warp threshold, wherein the second time warp threshold comprises a second percentage of a target delay length of packets stored in the memory storage unit; and

a second routine for generating a time warp indicator at a first value when the number of packets stored in the memory storage unit is less than a first time warp threshold, Wherein the first time warp threshold comprises a first percentage of a target delay length of packets stored in the memory storage unit and at a second value when the number of packets stored in the memory storage unit exceeds the second time warp threshold.

26. An apparatus, comprising:

a memory storage unit configured to store packets of data; and

a first controller configured to compare a number of packets stored in the memory storage unit to a first compression time warp threshold and a first expansion time warp threshold for the memory storage unit, wherein the first compression time warp threshold comprises a first percentage of a target delay length of packets stored in the memory storage unit and the first expression time warp threshold comprises a second percentage of a target delay length of packets stored in the memory storage unit, the first controller further adapted to generate a time warp control signal indicating compression if the number of stored packets exceeds the first compression time warp threshold and to generate a time warp control signal indicating expansion if the number of stored packets exceeds the first expansion time warp threshold.

27. The apparatus as in claim 26 , wherein the first controller is further configured to generate the time warp control signal for expansion if a next sequential packet is received after an anticipated playback time for the next sequential packet.

28. The apparatus as in claim 26 , wherein the first controller is further configured to average a status of the memory storage unit over a time window before comparing the number of stored packets to time warp thresholds.

29. The apparatus as in claim 26 , wherein the first controller is further configured to filter the number of packets stored in the memory storage unit over a time window.

30. The apparatus as in claim 29 , wherein the first controller is further configured to determine a target delay length, and determine the time window as a function of the target delay length.

31. The apparatus as in claim 26 , wherein the first controller is further configured to determine the target delay length as a target, number of packets to be stored in the memory storage unit.

32. The apparatus as in claim 26 , wherein the first controller is further configured to compare an average number of packets stored in the memory storage unit to the first expansion time warp threshold and the first compression time warp threshold.

33. The apparatus as in claim 26 , wherein the first controller is further configured to generate the time warp control signal is a multi-state control signal.

34. The apparatus as in claim 26 , wherein the first controller is further configured to determine a target delay length for the memory storage unit,

wherein the memory storage unit is an adaptive de-jitter buffer, and

wherein the target delay length is a target de-jitter buffer delay.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2005
From: BLACK, PETER JOHN; KAPOOR, ROHIT; SPINDOLA, SERAFIN DIAZ; YAVUZ, MEHMET
To: QUALCOMM INCORPORATED
Reel/Frame 016904/0252 →
Continuity (2)
Provisional Application 6060603600 · Aug 30, 2004
Related Publication 20060045138A1 · Mar 2, 2006