Integrated circuit system employing grain size enlargement
View Patent ↗An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a do pant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the substrate; and annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device.
1. A method of manufacture of an integrated circuit system comprising:
providing a substrate including an active device with a gate top surface exposed;
growing beyond the initial grain size of the gate material by implantation of a dopant within the gate material;
forming a dielectric layer over the active device and the substrate; and
annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device.
2. The method as claimed in claim 1 wherein:
implanting the dopant includes using a dopant dose above about 2×10 16 ions/cm 2 .
3. The method as claimed in claim 1 wherein:
implanting the dopant includes implanting germanium, antimony, or indium.
4. The method as claimed in claim 1 wherein:
forming the dielectric layer includes forming a tensile stressed layer or a compressive stressed layer.
5. The method as claimed in claim 1 wherein:
annealing the integrated circuit system includes creating stress within a channel of the active device that alters carrier mobility within the channel.
6. A method of manufacture of an integrated circuit system comprising:
providing a substrate including an active device;
forming a material layer over the active device and the substrate;
processing the material layer to expose a gate top surface;
growing beyond the initial grain size of the gate material by implantation of a dopant within the gate material;
forming a dielectric layer over the active device and the substrate; and
annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device.
7. The method as claimed in claim 6 wherein:
forming the material layer includes forming a resist layer or an oxide layer.
8. The method as claimed in claim 6 wherein:
foaming the material layer protects the substrate from the implantation of the dopant.
9. The method as claimed in claim 6 wherein:
processing the material layer includes an etchback or planarization process that utilizes the gate top surface for end point detection.
10. The method as claimed in claim 6 wherein:
implanting the dopant includes an implantation process with a sufficient energy and dose to amorphize and enlarge the grain size of the gate material.
11. A method of manufacture of an integrated circuit system comprising:
providing a substrate including an active device;
forming a material layer over the active device and the substrate;
processing the material layer to expose a gate top surface;
growing beyond the initial grain size of the gate material by implantation of germanium within the gate material;
forming a dielectric layer over the active device and the substrate; and
annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device.
12. The method as claimed in claim 11 wherein:
implanting germanium includes using a germanium dose sufficient to alter the drive current of the active device.
13. The method as claimed in claim 11 wherein:
implanting germanium includes using a germanium dose above about 2×10 16 ions/cm 2 .
14. The method as claimed in claim 11 wherein:
forming the dielectric layer includes forming a tensile stressed layer or a compressive stressed layer.
15. The method as claimed in claim 11 wherein:
annealing the integrated circuit system includes creating stress within a channel of the active device that alters carrier mobility within the channel.
16. The method as claimed in claim 11 wherein:
forming the material layer includes forming a resist layer or an oxide layer.
17. The method as claimed in claim 11 wherein:
forming the material layer protects the substrate from the implantation of germanium.
18. The method as claimed in claim 11 wherein:
processing the material layer includes an etchback or planarization process that utilizes the gate top surface for end point detection.
19. The method as claimed in claim 11 wherein:
implanting germanium includes implanting with a sufficient energy and dose to amorphize and enlarge the grain size of the gate material.
20. The method as claimed in claim 11 wherein:
providing the active device includes providing an n-channel field effect transistor.