IP Library Granted Patent US 7,834,827
Granted Patent B2
US 7,834,827 · App. 11/190,777 · Granted Nov 16, 2010

Light emitting device and driving method thereof

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 7,834,827
App. No.
11/190,777
Granted
Nov 16, 2010
Kind
B2
Abstract

According to a driving method of applying a reverse bias voltage, capacitance occurs due to a stacked structure of a conductor, an insulator and a conductor, or due to a structure of a TFT. This capacitance prevents normal operation. The invention provides a pixel configuration including at least a driving transistor for driving a light emitting element and a switching transistor for controlling the driving transistor, wherein the switching transistor is turned on in the case of applying a forward bias voltage after applying a reverse bias voltage. As a result, it is prevented that the potential changes due to unwanted capacitive coupling.

Claims (27)

1. A light emitting device comprising:

a light emitting element;

a first transistor for driving the light emitting element;

a second transistor for controlling the first transistor;

a capacitor between the gate electrode and one electrode of the first transistor;

a third transistor for discharging charges of the capacitor;

a fourth transistor between the first transistor and the light emitting element;

a unit for bringing a gate electrode of the first transistor into an electrically non-floating state by controlling the second transistor to be on-state in the case of applying a forward bias voltage to the light emitting element, after applying a reverse bias voltage to the light emitting element; and

a unit for determining a potential of the gate electrode of the first transistor so that the light emitting element emits no light,

wherein a gate electrode of the fourth transistor has a fixed potential.

2. The light emitting device according to claim 1 , further comprising:

an insulating film formed over one electrode of the first transistor,

wherein one electrode of the light emitting element is connected through a contact hole formed in the insulating film.

3. The light emitting device according to claim 1 , wherein one electrode of the light emitting element is formed over one electrode of the first transistor.

4. The light emitting device according to claim 1 , wherein the first transistor and the second transistor have a crystalline semiconductor film.

5. The light emitting device according to claim 1 , wherein the first transistor and the second transistor have an amorphous semiconductor film.

6. The light emitting device according to claim 1 , wherein the first transistor has a gate electrode and a low concentration impurity region overlapping the gate electrode.

7. A driving method of a light emitting device comprising a light emitting element, a first transistor for driving the light emitting element, and a second transistor for controlling the first transistor, comprising the steps of:

bringing a gate electrode of the first transistor into an electrically non-floating state by controlling the second transistor to be on-state in the case of applying a forward bias voltage to the light emitting element after applying a reverse bias voltage to the light emitting element; and

determining a potential of the gate electrode of the first transistor so that the light emitting element emits no light,

wherein a period during which all the scan lines are turned off is provided after a reverse bias voltage is applied to the light emitting element.

8. The driving method of a light emitting device, according to claim 7 , wherein a period during which the reverse bias voltage is applied comprises a period during which all scan lines are turned on before the reverse bias voltage is applied.

9. The driving method of a light emitting device, according to claim 7 , wherein an erasing period is provided before the period during which all the scan lines are turned on.

10. The driving method of a light emitting device, according to claim 7 ,

wherein the period of applying a reverse bias voltage is provided in one frame period;

the one frame period comprises m (m is a natural number of 2 or more) subframe periods SF 1 , SF 2 , . . . , SFm; and

the m subframe periods comprise writing periods Ta 1 , Ta 2 , . . . , Tam and display periods Ts 1 , Ts 2 , . . . , Tsm respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2005
From: MIYAKE, HIROYUKI; FUKUMOTO, RYOTA; IWABUCHI, TOMOYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 016823/0513 →
Priority Claims (1)
JP 2004-223024 · Jul 30, 2004 · national
Continuity (1)
Related Publication 20060022900A1 · Feb 2, 2006