IP Library Granted Patent US 7,842,616
Granted Patent B2
US 7,842,616 · App. 11/625,585 · Granted Nov 30, 2010

Methods for fabricating semiconductor structures

Assignee: Advanced Technology Development Facility, Inc.
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Quick Facts
Patent No.
US 7,842,616
App. No.
11/625,585
Granted
Nov 30, 2010
Kind
B2
Abstract

Methods for fabricating semiconductor structures are provided. A first layer may be deposited onto a substrate followed by the deposition of a second layer onto the first layer. A plurality of line structures may be etched in the second layer. A third layer, deposited onto the plurality of line structures of the second layer, may subsequently be etched to expose the plurality of line structures in the second layer. The plurality of line structures in the second layer may be removed, leaving an etched third layer. The etched third layer may be used as a mask to etch the first layer to form a semiconductor structure in the first layer. In some respects, the methods may include steps for etching the substrate using the etched first layer. The methods may also provide annealing the etched substrate to form a corrugate substrate surface.

Claims (15)

1. A method for fabricating a corrugated structure in a semiconductor surface, comprising:

providing a first semiconductor layer;

providing a second semiconductor layer on the first semiconductor layer, where the second semiconductor layer comprises a semiconductor substrate;

forming a plurality of line structures in the first semiconductor layer comprising:

depositing a third semiconductor layer on the first semiconductor layer;

etching the third semiconductor layer to create a plurality of line structures in the third semiconductor layer;

depositing a fourth semiconductor layer on the plurality of line structures in the etched third semiconductor layer

etching the fourth semiconductor layer to create a plurality of line structure in the fourth semiconductor layer;

removing the plurality of line structures in the third semiconductor layer;

depositing a fifth semiconductor layer on the plurality of line structures in the etched fourth semiconductor layer;

etching the semiconductor fifth layer to create a plurality of line structures in the fifth semiconductor layer;

removing the plurality of line structures in the fourth semiconductor layer; and

using the plurality of line structures in the fifth semiconductor layer as a mask to etch first layer to form a plurality of line structures in the first semiconductor layer;

using the plurality of line structure as a mask to etch the surface of the second semiconductor layer; and

annealing the etched second semiconductor layer in a hydrogen atmosphere to form the corrugated surface in the second semiconductor layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2015
From: ABOUND (BVI) LIMITED
To: SUZHOU TECHNOLOGY INSTITUTE FOR NANOTECH INDUSTRY
Reel/Frame 035768/0010 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2013
From: SVTC TECHNOLOGIES, LLC
To: ABOUND LIMITED
Reel/Frame 031045/0176 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INVENTOR'S NAME FROM --CAMBELL-- TO --CAMPBELL-- PREVIOUSLY RECORDED ON REEL 019144 FRAME 0858. ASSIGNOR(S) HEREBY CONFIRMS THE ENTIRE RIGHT, TITLE, AND INTEREST. Recorded Jun 1, 2007
From: IKEDA, SHUJI; WETZEL, JEFF; BEACH, JAMES; STAGER, CHARLES; GOTSKOWSKI, MICHAEL; CAMPBELL, ANDREW COLLIN
To: ADVANCED TECHNOLOGY DEVELOPMENT FACILITY, INC.
Reel/Frame 019369/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2007
From: IKEDA, SHUJI; WETZEL, JEFF; BEACH, JAMES; STAGER, CHARLES; CAMBELL, ANDREW COLLIN; GOTSKOWSKI, MICHAEL
To: ADVANCED TECHNOLOGY DEVELOPMENT FACILITY, INC.
Reel/Frame 019144/0858 →
Continuity (1)
Related Publication 20080176406A1 · Jul 24, 2008