Semiconductor memory cell and semiconductor memory array using the same

1. A semiconductor memory cell comprising a memory element including a first field effect transistor and a selection switch including a second field effect transistor, the memory element and the selection switch being connected in series,

wherein a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first field effect transistor and the second field effect transistor;

a first gate electrode of the first field effect transistor and a second gate electrode of the second field effect transistor are formed on the dielectric film;

on the semiconductor film, a drain electrode is formed outwardly of the first gate electrode, and a source electrode is formed outwardly of the second gate electrode;

under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween; and

ends of the semiconductor film that forms the channel are located inwardly of ends of the back-gate electrode.

2. The semiconductor memory cell of claim 1 , wherein a part of the ferroelectric film located under the first gate electrode is polarized in a first direction, and

a part of the ferroelectric film located under the second gate electrode is polarized in a second direction which is opposite to the first direction,

thereby resetting the semiconductor memory cell so that a part of the channel located under the first gate electrode has a low resistance and a part of the channel located under the second gate electrode has a high resistance.

3. The semiconductor memory cell of claim 2 , wherein a predetermined voltage is applied to the back-gate electrode to polarize the entire ferroelectric film in the first direction, and then a predetermined voltage is applied to the second gate electrode to polarize only the part of the ferroelectric film located under the second gate electrode in the second direction, thereby performing a reset of the semiconductor memory cell.

4. The semiconductor memory cell of claim 2 , wherein when the semiconductor memory cell is in a reset state, the first field effect transistor is in a normally on state, and the second field effect transistor is in a normally off state.

5. The semiconductor memory cell of claim 2 , wherein a predetermined voltage is applied to the back-gate electrode and between the first gate electrode and the drain electrode to polarize a part of the ferroelectric film located under the first gate electrode in the second direction which is opposite to a reset state, thereby writing data into the first field effect transistor.

6. The semiconductor memory cell of claim 1 , wherein a predetermined voltage is applied to the second gate electrode to turn the second field effect transistor on, and

a predetermined voltage is applied between the source electrode and the drain electrode to detect a current that flows in accordance with a polarization direction in a part of the ferroelectric film located under the first gate electrode, thereby reading data written into the first field effect transistor.

7. The semiconductor memory cell of claim 6 , wherein the voltage applied between the source electrode and the drain electrode is set so that a voltage applied to the ferroelectric film is equal to or lower than a coercive voltage of the ferroelectric film.

8. A semiconductor memory array, in which a plurality of the semiconductor memory cells of claim 1 are arranged in an array including rows and columns,

wherein in the semiconductor memory cells,

the first gate electrodes in each row are connected to a corresponding one of first word lines,

the second gate electrodes in each row are connected to a corresponding one of second word lines,

the source electrodes in each row are connected to a corresponding one of source lines,

the drain electrodes in each column are connected to a corresponding one of bit lines, and

the back-gate electrode is a common electrode in all of the semiconductor memory cells.

9. The semiconductor memory array of claim 8 , wherein a predetermined voltage is applied to the back-gate electrode to polarize, in a first direction, the entire ferroelectric film in all of the semiconductor memory cells, and then a predetermined voltage is applied between all of the second word lines and all of the source lines to polarize, in a second direction, only parts of the ferroelectric film located under the second gate electrodes in all of the semiconductor memory cells, thereby performing a reset operation.

10. The semiconductor memory array of claim 8 , wherein a predetermined voltage is applied between the back-gate electrode and the first word line in a selected row, and a predetermined voltage corresponding to data to be written is applied to each bit line, thereby writing the data into the first field effect transistor in each semiconductor memory cell in the selected row.

11. The semiconductor memory array of claim 10 , wherein after the data is written into a semiconductor memory cell, in which polarization direction of a part of the ferroelectric film located under the first gate electrode is opposite to that in a reset state, a voltage having the same magnitude as and opposite polarization to a write voltage is applied to the bit line connected to that semiconductor memory cell.

12. The semiconductor memory array of claim 8 , wherein a predetermined voltage is applied to the second word line in a selected row, and a predetermined voltage is applied to each bit line to detect a current that flows in the source line in the selected row, thereby reading data written into each semiconductor memory cell in the selected row.