Electrostatic discharge protection device for an integrated circuit

1. An integrated circuit formed in a semiconductor material comprising:

a protected terminal;

a transistor connected to the protected terminal and forming a parasitic element capable of triggering itself under an effect of an electrostatic discharge applied to the protected terminal; and

a protection device formed so as to be biased at the same time as the parasitic element under the effect of the electrostatic discharge, the protection device being positioned to channel an electrostatic discharge current more readily than the parasitic element.

2. The integrated circuit according to claim 1 further comprising a bias connection, wherein the protection device is located further from the bias connection of the semiconductor material than the parasitic element is from the bias connection, so as to be biased more than the parasitic element.

3. The integrated circuit according to claim 1 wherein the parasitic element and the protection device have a common junction produced by a doped region formed in the semiconductor material and connected to the protected terminal.

4. The integrated circuit according to claim 1 wherein the transistor is a MOS transistor having a drain formed by a doped region connected to the protected terminal, and the parasitic element is a bipolar transistor.

5. The integrated circuit according to claim 1 wherein the protection device comprises a bipolar protection transistor connected to the protected terminal.

6. The integrated circuit according to claim 5 wherein the parasitic element and the protection transistor are biased by a same bias connection of the semiconductor material.

7. The integrated circuit according to claim 5 wherein the transistor includes a first doped region and the protection transistor is formed in the semiconductor material and includes a second doped region separated from the first doped region by an insulator.

8. The integrated circuit according to claim 7 wherein the insulator is formed in a trench.

9. The integrated circuit according to claim 5 comprising a resistance inserted between the protected terminal and a terminal of the parasitic element.

10. The integrated circuit according to claim 1 wherein the protection device comprises a thyristor connected to the protected terminal.

11. The integrated circuit according to claim 10 wherein the thyristor comprises a pnp transistor, and an npn bipolar transistor, the npn transistor comprising a collector linked to the protected terminal and a base located further from a bias connection of the semiconductor material than the parasitic element is located from the bias connection.

12. A method comprising:

forming an integrated circuit in a semiconductor material including an transistor connected to a protected terminal and a parasitic element capable of triggering itself under an effect of an electrostatic discharge applied to the protected terminal;

forming in the semiconductor material a protection device connected to the protected terminal; and

channeling an electrostatic discharge current through the protection device more than through the parasitic element.

13. The method according to claim 12 wherein the protection device is biased at the same time as the parasitic element with a stronger bias than the parasitic element.

14. The method according to claim 12 wherein the protection device is produced using a junction of the parasitic element, the junction being produced by a first doped region formed in the semiconductor material and connected to the protected terminal.

15. The method according to claim 12 wherein the output transistor is a MOS transistor having a drain formed by a first doped region connected to the protected terminal, and the parasitic element is a bipolar transistor.

16. The method according to claim 12 wherein the protection device comprises a bipolar protection transistor connected to the protected terminal.

17. The method according to claim 16 wherein a terminal of the parasitic element and a terminal of the protection transistor are biased by a same bias connection of the semiconductor material.

18. The method according to claim 16 wherein the protection transistor is formed in the semiconductor material by a second doped region separated from the first region by an insulator.

19. The method according to claim 16 , comprising inserting a resistance between the protected terminal and a terminal of the parasitic element.

20. The method according to claim 12 , comprising a step of forming in the semiconductor material a thyristor connected to the protected terminal.

21. The method according to claim 20 wherein the thyristor comprises a bipolar transistor of pnp type, and a bipolar transistor of npn type, the npn-type transistor comprising a collector linked to the protected terminal and a base located further from a bias connection of the semiconductor material than the parasitic element.

22. An integrated circuit formed in a semiconductor, the integrated circuit comprising:

a transistor;

a protected terminal connected to the transistor;

a parasitic element connected to the protected terminal;

a bias connection coupled to a control terminal of the parasitic element; and

an electrostatic discharge protection device connected to the protected terminal and located in the semiconductor further from the bias connection than the parasitic element is from the bias connection.

23. The integrated circuit of claim 22 wherein the protection device is a bipolar transistor.

24. The integrated circuit of claim 23 wherein the transistor is an MOS transistor and the parasitic element is a bipolar transistor.

25. The integrated circuit of claim 22 wherein the protection device is a thyristor.