Stratified underfill method for an IC package

1. A method of forming semiconductor package comprising:

joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board, the low-k dielectric layer having a dielectric constant of about 3.0 or less, the solder bumps having a lead concentration of about 5% or less; and

forming a stratified underfill layer between the die and the package substrate or printed circuit board.

2. The method of claim 1 , wherein the stratified underfill layer includes an underfill material and a filler material.

3. The method of claim 2 , wherein the forming includes:

dispensing a mixture of the underfill material and the filler material between the die and the package substrate;

allowing the filler material to at least partially settle after the dispensing step; and

curing the underfill material after the filler material at least partially settles.

4. The method of claim 3 , wherein the filler particles are distributed with a gradient after partially settling.

5. The method of claim 2 , wherein the filler material comprises first and second filler particles, the first particles having a larger particle size than the second particles.

6. The method of claim 5 , wherein the forming step includes:

mixing the underfill material and the first and second filler particles to form a mixture; and

dispensing the mixture between the die and the package substrate or printed circuit board.

7. The method of claim 5 , wherein:

the stratified underfill has the first filler particles adjacent the integrated circuit die and the second filler particles adjacent the package substrate or print circuit board.

8. The method of claim 1 , wherein the stratified underfill includes a first underfill layer between the die and the package substrate or printed circuit board; and

a buffer layer between the first underfill layer and the integrated circuit die.

9. The method of claim 1 , wherein the forming step comprises:

forming a first layer of an underfill material contacting the package substrate or printed circuit board, the first layer having a thickness less than a size of a first gap between the die and the package substrate or printed circuit board, and

dispensing a molding compound to form a second layer that fills a second gap between the die and the first layer, to encapsulate the die.

10. The method of claim 1 , wherein, the low-k dielectric layer has a dielectric constant less than 2.75.

11. The method of claim 1 , wherein:

the stratified underfill layer comprises a first layer and a second layer with substantially different coefficients of thermal expansion (CTE) from each other.

12. The method of claim 11 , wherein the first layer is adjacent to the integrated circuit die and has a CTE<10 ppm/C.

13. The method of claim 12 , wherein the second layer is adjacent to the package or printed circuit board and has a CTE>10 ppm/C.

14. A method of forming a semiconductor package comprising the steps of:

joining an integrated circuit die to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board;

mixing a filler material in an underfill material to form a mixture,

dispensing the mixture to substantially fill a gap between the die and the package substrate or printed circuit board,

allowing the filler material to at least partially settle after the dispensing step; and

curing the underfill material after the filler material at least partially settles.

15. The method of claim 14 , wherein:

the filler material comprises first filler particles and second filler particles, the first filler particles having a larger particle size than the second filler particles.

16. The method of claim 14 , wherein, the low-k dielectric layer has a dielectric constant of about 3.0 or less, and the solder bumps have a lead concentration of about 5% or less.

17. The method of claim 16 , wherein, the low-k dielectric layer has a dielectric constant less than 2.75.

18. A method of forming a semiconductor package comprising the steps of:

applying a first underfill material over a wafer having a plurality of integrated circuit dies thereon;

joining one of the integrated circuit dies from the wafer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board;

dispensing a second underfill layer to substantially fill a gap between the first underfill material on the one integrated circuit die and the package substrate or printed circuit board, the first and second underfill materials having different coefficients of thermal expansion from each other, wherein, the one integrated circuit die has an inter-layer dielectric layer comprising a low-k dielectric material with a dielectric constant of about 3.0 or less, and the solder bumps have a lead concentration of about 5% or less.

19. The method of claim 18 , wherein the applying step includes one of the group consisting of printing or spin coating.