Inverter, logic circuit including an inverter and methods of fabricating the same
An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.
1. An inverter, comprising:
a load transistor of a depletion mode, the load transistor having a first oxide layer as a first channel layer; and
a driving transistor of an enhancement mode, the driving transistor being connected to the load transistor and having a second oxide layer as a second channel layer,
wherein the driving transistor includes,
a source electrode and a drain electrode both corresponding to the second oxide layer, and
a barrier layer between the second oxide layer and the source electrode and the drain electrode, the barrier layer having a work function greater than that of the second oxide layer.
2. The inverter of claim 1 , wherein the barrier layer is at least one selected from the group consisting of a titanium (Ti) oxide layer, a copper (Cu) oxide layer, a nickel (Ni) oxide layer, a Ni oxide layer doped with Ti, a ZnO-based oxide layer, a ZnO-based oxide layer doped with at least one of I, II and V-group elements, a ZnO-based oxide layer doped with silver (Ag) and combinations thereof.
3. The inverter of claim 1 , wherein the first oxide layer and the second oxide layer are layers of the same material.
4. The inverter of claim 1 , wherein the first oxide layer and the second oxide layer have different carrier concentrations.
5. The inverter of claim 4 , wherein the second oxide layer has a carrier concentration lower than that of the first oxide layer.
6. The inverter of claim 1 , wherein at least one of the first oxide layer and the second oxide layer includes a ZnO-based material.
7. The inverter of claim 1 , wherein at least one of the load transistor and the driving transistor is a thin film transistor having a bottom gate structure.
8. The inverter of claim 1 , wherein at least one of the load transistor and the driving transistor is a thin film transistor having a top gate structure.
9. A logic circuit comprising the inverter according to claim 1 .
10. The logic circuit of claim 9 , wherein the logic circuit is a not-and (NAND) circuit, a not-or (NOR) circuit, an encoder, a decoder, a multiplexer (MUX), a demultiplexer (DEMUX) or a sense amplifier.