Method and apparatus for improving SRAM write operations
A memory cell includes an access transistor, first and second pull-up transistors, first and second pull-down transistors, and a first search transistor. The access transistor is connected to a first word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the first data node, and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and the first data node, and the second pull-down transistor is connected to the second power supply point and the second data node. The first search transistor is connected to the second data node and includes a source terminal connected to a third power supply point comprising a voltage less than the voltage at the second power supply point.
1. A memory cell, comprising:
an access transistor, wherein the access transistor is connected to a first word line and connected between a first bit line and a first data node;
first and second pull-up transistors, wherein the first pull-up transistor is connected to a first power supply point and to the first data node, and wherein the second pull-up transistor is connected to the first power supply point and the second data node;
first and second pull-down transistors, wherein the first pull-down transistor is connected to a second power supply point and to the first data node, and wherein the second pull-down transistor is connected to the second power supply point and to the second data node; and
a first search transistor connected to the second data node and comprising a source terminal connected to a third power supply point comprising a voltage less than the voltage at the second power supply point.
2. The memory cell of claim 1 , wherein the access transistor, first and second pull-up transistors, first and second pull-down transistors, and first search transistors comprise junction field effect transistors.
3. The memory cell of claim 1 , wherein the first power supply point comprises a voltage of 0.5 volts.
4. The memory cell of claim 1 , wherein the second power supply point comprises a voltage of 0 volts.
5. The memory cell of claim 1 , wherein the third power supply point comprises a voltage of −0.3 volts during one or more write operations.
6. The memory cell of claim 1 , wherein the third power supply point is switched to a voltage of −0.3 volts during one or more write operations.
7. The memory cell of claim 6 , wherein the third power supply point is switched when writing a logical 1 to the cell.
8. The memory cell of claim 1 , wherein the memory cell can perform a read operation, a write operation, or reside in an idle state.
9. The memory cell of claim 1 , wherein the memory cell comprises a second search transistor connected to the first search transistor to implement a ternary content addressable memory cell.