Interrupt controller for accelerated interrupt handling in a data processing system and method thereof
A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
1. A data processing system comprising:
a processor; and
an interrupt controller coupled to the processor, wherein the interrupt controller receives an interrupt request from an interrupt source, assigns a priority to the interrupt request, assigns a priority to the interrupt request, assigns an interrupt vector to the interrupt request, sets a state of the interrupt request to pending, and provides the interrupt request, the interrupt identifier corresponding to the interrupt request, and the interrupt vector corresponding to the interrupt request to the processor when the interrupt request is a to priority interrupt request as compared to other pending interrupt requests for the processor, and wherein the processor, upon accepting the interrupt request, provides to the interrupt controller an interrupt acknowledge corresponding to the interrupt request and the interrupt identifier corresponding to the interrupt request.
2. The data processing system of claim 1 , wherein the interrupt controller is coupled to the processor via an asynchronous interface, and wherein the interrupt request, interrupt identifier, interrupt vector, and interrupt acknowledge are provided via the asynchronous interface.
3. The data processing system of claim 1 , wherein the processor, upon accepting the interrupt request, also asserts an interrupt taken/not taken indicator to indicate that the interrupt request was accepted by the processor, wherein the interrupt taken/not taken indicator is provided from the processor to the interrupt controller.
4. The data processing system of claim 1 , wherein when the interrupt request is the top priority interrupt, the interrupt controller generates the interrupt identifier, and stores the interrupt identifier in an outstanding interrupt queue.
5. The data processing system of claim 1 , wherein the interrupt controller operates according to a first clock and the processor operates according to a second clock wherein the first clock has an arbitrary phase and frequency relationship with the second clock.
6. The data processing system of claim 3 , wherein the processor, upon not accepting the interrupt request, also negates the interrupt taken/not taken indicator to indicate that the interrupt was not accepted by the processor.
7. The data processing system of claim 4 , wherein when the interrupt request is the top priority interrupt request, the interrupt controller also stores a source identifier corresponding to the interrupt source in the outstanding interrupt queue.
8. The data processing system of claim 4 , wherein the interrupt controller, upon receiving the interrupt acknowledge and the interrupt identifier from the processor, uses the interrupt identifier to locate a matching entry within the outstanding interrupt request queue which matches the interrupt identifier.
9. The data processing system of claim 8 , wherein the interrupt controller, upon receiving the interrupt acknowledge and the interrupt identifier from the processor, provides a state update indicator to change the state of the interrupt request from pending to in-service.
10. A method within a data processing system having a processor, the method comprising:
providing to the processor an interrupt request, an interrupt identifier corresponding to the interrupt request, and an interrupt vector corresponding to the interrupt request;
receiving from the processor, when the interrupt request is accepted by the processor, an interrupt acknowledge corresponding to the interrupt request and the interrupt identifier; and
receiving from the processor an interrupt taken/not taken indicator, wherein the processor asserts the interrupt taken/not taken indicator to indicate that the interrupt request was accepted by the processor and the processor negates the interrupt taken/not taken indicator to indicate that the interrupt request was not accepted by the processor.
11. The method of claim 10 , wherein prior to the providing to the processor, the method further comprises:
receiving the interrupt request from an interrupt source;
assigning a priority and the interrupt vector to the interrupt request;
setting a state of the interrupt request to pending; and
sorting the interrupt request among other pending interrupt requests for the processor to identify a top priority interrupt request, wherein the providing to the processor is performed when the interrupt request is identified as the top priority interrupt request.
12. The method of claim 11 , further comprising:
when the interrupt request is identified as the top priority interrupt request, generating the interrupt identifier and storing the interrupt identifier in a first entry of an outstanding interrupt queue.
13. The method of claim 12 , further comprising:
when the interrupt request is identified as the top priority interrupt request, storing a source identifier corresponding to the interrupt source in the first entry of the outstanding interrupt queue.
14. The method of claim 12 , further comprising:
after the receiving from the processor the interrupt acknowledge and the interrupt identifier, using the interrupt identifier to locate a matching entry within the outstanding interrupt request queue which matches the interrupt identifier.
15. The method of claim 14 , further comprising:
when the matching entry is located within the outstanding interrupt request queue, changing the state of the interrupt request from pending to in-service and removing the matching entry from the outstanding interrupt request queue.
16. A method within a data processing system having a processor, the method comprising:
receiving a first interrupt request from a first interrupt source;
setting a state of the first interrupt request to pending;
generating a first interrupt request identifier corresponding to the first interrupt request;
storing the first interrupt request identifier in an outstanding interrupt request queue;
providing to a processor the first interrupt request, the first interrupt identifier, and a first interrupt vector corresponding to the first interrupt request; and
receiving from the processor, when the first interrupt request is accepted by the processor, a first interrupt acknowledge corresponding to the first interrupt request and the first interrupt identifier.
17. The method of claim 16 , further comprising:
after the receiving from the processor the first interrupt acknowledge and the first interrupt identifier, using the first interrupt identifier to locate a matching entry within the outstanding interrupt request queue which matches the interrupt identifier; and
when the matching entry is located within the outstanding interrupt request queue, changing the state of the first interrupt request from pending to in-service.
18. The method of claim 16 , wherein prior to the receiving from the processor, the method further comprises:
receiving a second interrupt request from a second interrupt source;
setting a state of the second interrupt request to pending; and
when the second interrupt request has a higher priority than the first interrupt request, the method further comprises:
generating a second interrupt request identifier corresponding to the second interrupt request;
storing the second interrupt request identifier in the outstanding interrupt request queue; and
providing to the processor the second interrupt request, the second interrupt identifier, and a second interrupt vector corresponding to the second interrupt request.