Signal decoding method and device, and signal storage system
An LDPC unit decoder included in a signal decoding device is provided with a parity checking unit that is a multiplier for performing multiplication of a check matrix (parity check matrix) and temporary estimated values of an encoded signal, computed by a temporary estimated value computation unit. A check matrix holding unit holds the check matrix. If s and t are natural numbers, s≧t≧2, among s columns extracted from this check matrix, t columns or less have a linearly independent relationship. These s columns are multiplied at locations where error occurrence frequency is relatively high, with regard to the temporary estimated values. According to this mode, the matrix is composed to include t columns that are linearly independent, that is, t columns that are not linearly dependent.
1. A signal decoding device comprising a unit decoder for performing, when an input signal series is acquired and the input signal series is decoded, multiplication of the signal series, that is decoded, by a matrix;
wherein if s and t are natural numbers, with s≧t≧2, the unit decoder uses the matrix in which, among s columns extracted from the matrix, t columns or less have a linearly independent relationship, and the s columns are multiplied by a signal in which error occurrence frequency is relatively high in the decoded signal series; and
wherein the value of the t is decided based on a tolerance limit of an error occurring in the signal belonging to the decoded signal series, that cannot be detected when decoding.
2. A signal decoding device comprising a unit decoder for performing, when an input signal series is acquired and the input signal series is decoded, multiplication of the signal series, that is decoded, by a matrix;
wherein if s and t are natural numbers, with s≧t≧2, the unit decoder uses the matrix in which, among s columns extracted from the matrix, t columns or less have a linearly independent relationship, and the s columns are multiplied by a signal in which error occurrence frequency is relatively high in the decoded signal series; and
wherein the unit decoder decodes the encoded signal using a low density parity check code.
3. A signal decoding device comprising a unit decoder for performing, when an input signal series is acquired and the input signal series is decoded, multiplication of the signal series, that is decoded, by a matrix;
wherein, ifs and t are natural numbers, with s≧t≧2, the unit decoder uses the matrix in which, among s columns extracted from the matrix, t columns or less have a linearly independent relationship, and the s columns are adjacent in the matrix; and
wherein the value of the t is decided based on a tolerance limit of an error occurring in the signal belonging to the decoded signal series, that cannot be detected when decoding.
4. A signal decoding device comprising a unit decoder for performing, when an input signal series is acquired and the input signal series is decoded, multiplication of the signal series, that is decoded, by a matrix;
wherein, ifs and t are natural numbers, with s≧t≧2, the unit decoder uses the matrix in which, among s columns extracted from the matrix, t columns or less have a linearly independent relationship, and the s columns are adjacent in the matrix; and
wherein the unit decoder decodes the encoded signal using a low density parity check code.
5. A signal decoding device comprising a unit decoder for performing, when an input signal series is acquired and the input signal series is decoded, multiplication of the signal series that is decoded, by a matrix of m rows and n columns, m and n being natural numbers, with m and n≧2, wherein,
the matrix includes a first and a second partial matrix of m rows and s columns, s being a natural number, with n>s, linked in a columnar direction, and, in the first and the second partial matrices, among the s columns thereof, t columns or less, t being a natural number, with s≧t≧2, have a linearly independent relationship.
6. A signal decoding device according to claim 5 , wherein the value of the t is decided based on a tolerance limit of an error occurring in the signal belonging to the decoded signal series, that cannot be detected when decoding.
7. A signal decoding device according to claim 6 , wherein the shift processing comprises row replacement.
8. A signal decoding device according to claim 5 , wherein the unit decoder decodes the encoded signal using a low density parity check code.
9. A signal decoding device according to claim 5 , wherein the second partial matrix has a relationship in which prescribed shift processing is applied, with respect to elements of the first partial matrix.
10. A signal storage system having a write channel and a read channel, wherein
the write channel comprises:
a first encoder for run-length encoding of data;
a second encoder for further encoding data encoded by the first encoder, using a low density parity check code; and
a writing unit for writing the data encoded by the second encoder, to the storage device;
the read channel comprises:
a reading unit for reading the data encoded by the second encoder, from the storage device;
a soft output detection unit for calculating likelihood for the data read by the reading unit and for outputting a soft decision value;
a second decoder, corresponding to the second encoder, for decoding the data outputted from the soft output detection unit; and
a first decoder, corresponding to the first encoder, for further decoding the data decoded by the second decoder;
and wherein
the second decoder has a unit decoder that, when the data outputted from the soft output detection unit is decoded, performs multiplication of the decoded data by a matrix;
if s and t are natural numbers, s≧t≧2, the unit decoder uses a matrix in which, among s columns extracted from the matrix, t columns or less have a linearly independent relationship; and
the s columns are multiplied by a portion of the decoded data in which error occurrence frequency is relatively high.
11. A signal storage system according to claim 10 , the system further comprising:
a storage device for storing prescribed data; and
a controller for controlling writing of data to the storage device, and reading of data from the storage device; wherein
the read channel reads, according to an instruction of the controller, data stored in the storage device; and
the write channel writes, according to an instruction of the controller, prescribed data to the storage device.
12. A signal storage system according to claim 10 , wherein the system is integrated on at least one semiconductor board.
13. A signal storage system having a write channel and a read channel, wherein
the write channel comprises:
a first encoder for run-length encoding of data;
a second encoder for further encoding data encoded by the first encoder, using a low density parity check code; and
a writing unit for writing the data encoded by the second encoder to the storage device;
the read channel comprises:
a reading unit for reading the data encoded by the second encoder, from the storage device;
a soft output detection unit for calculating likelihood for the data read by the reading unit and for outputting a soft decision value;
a second decoder, corresponding to the second encoder, for decoding the data outputted from the soft output detection unit; and
a first decoder, corresponding to the first encoder, for further decoding the data decoded by the second decoder; and wherein
the second decoder has a unit decoder that, when the data outputted from the soft output detection unit is decoded, performs multiplication of the decoded data by a matrix;
if s and t are natural numbers, s≧t≧2, the unit decoder uses a matrix in which, among s columns extracted from the matrix, t columns or less have a linearly independent relationship; and
the s columns are adjacent in the matrix.
14. A signal storage system according to claim 13 , the system further comprising:
a storage device for storing prescribed data; and
a controller for controlling writing of data to the storage device, and reading of data from the storage device; wherein
the read channel reads, according to an instruction of the controller, data stored in the storage device; and
the write channel writes, according to an instruction of the controller, prescribed data to the storage device.
15. A signal storage system according to claim 13 , wherein the system is integrated on at least one semiconductor board.