Efficient transistor structure
An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.
1. An integrated circuit comprising:
a first source;
a first drain;
a second source;
a first gate arranged between said first source and said first drain;
a second gate arranged between said first drain and said second source,
wherein said first and second gates define alternating first and second regions in said drain, wherein said first and second gates are arranged farther apart in said first regions than in said second regions; and
a well substrate contact arranged in said first regions.
2. An integrated circuit comprising:
a first source;
a first drain;
a second source;
a first gate arranged between said first source and said first drain;
a second gate arranged between said first drain and said second source,
wherein said first and second gates define alternating first and second regions in said drain, wherein said first and second gates are arranged farther apart in said first regions than in said second regions; and
R well substrate contacts arranged in said first regions, where R is an integer greater than one.
3. The integrated circuit of claim 2 wherein R is an integer that is greater than three and less than seven.
4. The integrated circuit of claim 1 wherein said integrated circuit includes a plurality of transistors.
5. The integrated circuit of claim 4 wherein said transistors include PMOS transistors.
6. The integrated circuit of claim 2 herein said R well substrate contacts are associated with respective ones of R transistors.
7. An integrated circuit comprising:
a first source;
a first drain;
a second source;
a first gate arranged between said first source and said first drain;
a second gate arranged between said first drain and said second source,
wherein said first and second gates define alternating first and second regions in said drain, wherein said first and second gates are arranged farther apart in said first regions than in said second regions;
a second drain; and
a third gate arranged between said second source and said second drain,
wherein said second and third gates define alternating third and fourth regions, said second and third gates are arranged farther apart in said third regions than in said fourth regions,
wherein said first regions are arranged adjacent to said fourth regions and said second regions are arranged adjacent to said third regions, and
wherein said first and third regions include R well substrate contacts and R is an integer greater than one.
8. A method for providing an integrated circuit comprising:
providing a first source;
providing a first drain;
providing a second source;
locating a first gate between said first source and said first drain;
locating a second gate between said first drain and said second source;
defining alternating first and second regions in said drain using said first and second gates;
arranging said first and second gates farther apart in said first regions than in said second regions; and
locating a well substrate contact in said first regions.
9. A method for providing an integrated circuit comprising:
providing a first source;
providing a first drain;
providing a second source;
locating a first gate between said first source and said first drain;
locating a second gate between said first drain and said second source;
defining alternating first and second regions in said drain using said first and second gates;
arranging said first and second gates farther apart in said first regions than in said second regions; and
locating R well substrate contacts in said first regions, where R is an integer greater than one.
10. The method of claim 9 wherein R is an integer that is greater than three and less than seven.
11. The method of claim 8 wherein said integrated circuit includes a plurality of transistors.
12. The method of claim 11 wherein said transistors include PMOS transistors.
13. The method of claim 9 further comprising associating said R well substrate contacts with respective ones of R transistors.
14. A method for providing an integrated circuit comprising:
providing a first source;
providing a first drain;
providing a second source;
locating a first gate between said first source and said first drain;
locating a second gate between said first drain and said second source;
defining alternating first and second regions in said drain using said first and second gates;
arranging said first and second gates farther apart in said first regions than in said second regions;
providing a second drain;
providing a third gate between said second source and said second drain;
defining alternating third and fourth regions using said second and third gates;
arranging said second and third gates farther apart in said third regions than in said fourth regions; and
arranging said first regions adjacent to said fourth regions and said second regions adjacent to said third regions,
wherein said first and third regions include R well substrate contacts, where R is an integer greater than one.