Processing elements grouped in MIMD sets each operating in SIMD mode by controlling memory portion as instruction cache and GPR portion as tag
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P<S, operate as an instruction cache. The remaining memories operate as data memories or as data cache memories. One out of S sets of general-purpose registers, inherently belonging to the PEs, directly operates as a general register group for the PU. Out of the remaining S−1 sets, T set or a required number of sets, where T<S−1, are used as storage registers that store tags of the instruction cache.
1. A mixed mode parallel processor system comprising:
N number of processing elements,
the N number of processing elements performing parallel operations in SIMD operation;
the N number of the processing elements being grouped into M (=N÷S) sets (where S and M are natural numbers not smaller than 2) of processing units, in MIMD operation, each of the M sets of processing units including S number of the processing elements, each of S number of the processing elements in each of the M sets of processing units including memory resources and general-purpose register resources, the M sets of processing units performing parallel operations with one another, and the S number of processing elements performing parallel operations with one another, wherein in MIMD operation, part of the memory resources of each of the M sets of processing units operate as an instruction cache memory;
part of the general-purpose register resources in each of the M sets of processing units operate as a tag storage area of an instruction cache and each of the M sets of processing units includes a control circuit performing, for the S number of the processing elements in each of the M sets of processing units, instruction cache control and instruction sequence control.
2. The mixed mode parallel processor system according to claim 1 , wherein, in each of the M sets of processing units, in MIMD operation,
P number (P<S) memory resources out of S number of the memory resources belonging to S number of the processing elements, operate as instruction cache memories, with the remaining S-P number of memory resources operating as data memories or as data cache,
one set out of S sets of the general-purpose register resources, belonging to S number of the processing elements, directly operating as the general-purpose register resources of one processing unit associated therewith, and T set (T<S−1) or a predetermined constant number out of the remaining S−1 sets, operating as tag storage resources of an instruction cache, with the remaining sets operating as tag storage resources of a data cache in case of using the data cache.
3. The mixed mode parallel processor system according to claim 1 , comprising
a control processing element for controlling an entire system; wherein in each of M sets of processing units,
one of S number of the processing elements, having memory resources that operate as the instruction cache memory in MIMD operation, includes
the control circuit; and
an instruction stream selector that selects an instruction from the control processing element or an instruction from the instruction cache memory,
the processing elements not including the instruction cache memory, out of S number of the processing elements, receiving and executing the instruction from the instruction stream selector in MIMD operation.
4. The mixed mode parallel processor system according to claim 1 , comprising
a control processing element for global control, wherein
in each of the M sets of processing units,
each of S number of the processing elements includes:
the control circuit; and
an instruction stream selector; and wherein
in MIMD operation, the instruction stream selector of one of the processing elements, including the instruction cache memory, out of S number of the processing elements, selects an instruction from the control processing element or an instruction from the instruction cache memory,
the remaining processing elements, not including the instruction cache memory, receiving and executing the instruction from the instruction stream selector of the sole processing element including the instruction cache memory.
5. A mixed mode parallel processor method for a mixed mode parallel processor system including:
N number of processing elements, the N number of processing elements being grouped into M (=N÷S) sets (where S and M are natural numbers not smaller than 2) of processing units, each of the M sets of processing units including S number of the processing elements, each of the S number of the processing elements in each of the M sets of processing units including memory resources and general-purpose register resources, in MIMD operation, the method comprising:
the N number of processing elements performing parallel operations in SIMD operation;
the M sets of the processing units performing parallel operations with one another, and the S number of the processing elements performing parallel operations with one another in MIMD operation;
a part of the memory resources of each of the M sets of processing units operating as instruction cache memories in MIMD operation;
the general-purpose register resources of each of the M sets of processing units operating as a tag storage area of an instruction cache, in MIMD operation; and
a control circuit in each of the M sets of processing units performing, for the S number of the processing elements in each of the M sets of processing units, instruction cache control and instruction sequence control.
6. The mixed mode parallel processor method according to claim 5 , comprising:
in each of the M sets of the processing units, in MIMD operation:
P number (P<S) of the memory resources, out of S number of the memory resources belonging to S number of processing elements, operating as instruction cache memories, and the remaining S-P number of memory resources operating as data memories or as data cache memories;
one set out of S sets of the general-purpose register resources, belonging to S number of the processing elements, directly operating as the general-purpose register resources of the processing unit, and
T set (T<S−1) or a predetermined constant number out of the remaining S−1 sets, operating as tag storage resources of an instruction cache, and the remaining sets operating as tag storage resources of a data cache in case of using a data cache.
7. The mixed mode parallel processor method according to claim 5 comprising:
the instruction stream selector of the one processing element in the processing unit, including the instruction cache memory, selecting an instruction from the control processing element for global control or an instruction from the instruction cache memory; and
the remaining processing elements not including the instruction cache memory receiving and executing the instruction from the instruction stream selector during the MIMD operation.
8. The mixed mode parallel processor method according to claim 5 , comprising:
the instruction stream selector of the sole processing element in the processing unit, including the instruction cache memory, selecting, during the MIMD operation, an instruction from the control processing element for global control or an instruction from the instruction cache memory; and
the remaining processing elements, not including the instruction cache memory, receiving and executing the instruction from the instruction stream selector of the sole processing element including the instruction cache memory.
9. Computer readable storage medium storing mixed mode parallel processor program for a mixed mode parallel processor system, the system including N number of processing elements, N number of the processing elements being grouped into M (=N÷S) sets (where S and M are natural numbers not smaller than 2) of processing units, each of the M sets of processing units including S number of the processing elements, each of the M sets of processing units including memory resources and general-purpose register resources in the S number of the processing elements, in MIMD operation, the program causing the mixed mode parallel processor system to execute:
a step of the N number of the processing elements performing parallel operations in SIMD operation; and
a step of the M sets of the processing units performing parallel operations with one another, and the S number of the processing elements performing parallel operations with one another, in MIMD operation;
a step of part of the memory resources of each of the M sets of processing units operating as instruction cache memories in MIMD operation;
a step of the general-purpose register resources of each of the M sets of processing units operating as tag storage area of an instruction cache in MIMD operation; and
a step of a control circuit in each of the M sets of processing units performing, for the S number of the processing elements in each of the M sets of processing units, instruction cache control and instruction sequence control.
10. Computer readable storage medium storing the mixed mode parallel processor program according to claim 9 , further causing the mixed mode parallel processor system to execute:
a step of P (P<S) of S memory resources, respectively belonging to S number of the processing elements, in each of the M sets of the processing units, operating as instruction cache memories, and the remaining S-P memory resources operating as data memories or as data cache memories, in MIMD operation;
a step of one set of S sets of the general-purpose register resources, respectively belonging to S number of the processing elements, directly operating as the general-purpose register resources of the processing units; and
a step of T set (T<S−1) or a predetermined constant number out of the remaining S−1 sets, operating as tag storage resources of an instruction cache, and the remaining sets operating as tag storage resources of a data cache in case of using a data cache.