Configurable processor module accelerator using a programmable logic device

1. An accelerator module, comprising:

a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory;

the first programmable logic device having access to a bitstream;

the bitstream capable of being stored in the first memory;

the access by the first programmable logic device to the bitstream being controlled by the controller;

the bitstream capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with a motherboard using a microprocessor interface of the motherboard;

the transport interface capable of direct communication via the microprocessor interface with a microprocessor located on the motherboard; and

the circuit board configured for interconnecting the first programmable logic device to the microprocessor interface.

2. The accelerator module according to claim 1 , wherein the controller is configured to monitor the first programmable logic device and configured to cause instantiation of the transport interface in the first programmable logic device responsive to a detected condition.

3. The accelerator module according to claim 1 , further comprising:

a second memory coupled to the circuit board;

the bitstream capable of being instantiated in the first programmable logic device using the programmable logic thereof to additionally provide at least a memory interface for communication with the second memory; and

the circuit board configured for directly interconnecting the first programmable logic device and the controller to the microprocessor interface.

4. The accelerator module according to claim 3 , wherein:

the second memory is Static Random Access Memory (“SRAM”); and wherein the second memory interface is an SRAM interface;

the first memory interface is flash memory; and

the controller is a second programmable logic device.

5. The accelerator module according to claim 4 , wherein the first programmable logic device is a Field Programmable Gate Array; and wherein the second programmable logic device is a Complex Programmable Logic Device.

6. An accelerator module, comprising:

a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory;

the first programmable logic device having access to a bitstream;

the bitstream capable of being stored in the first memory;

the access to the bitstream by the first programmable logic device being controlled by the controller;

the bitstream capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with a motherboard using a microprocessor interface of the motherboard; and

the circuit board configured for interconnecting the first programmable logic device and the controller to the microprocessor interface.

7. The accelerator module according to claim 6 , wherein:

the transport interface is capable of direct communication via the microprocessor interface with a second memory located on the motherboard; and

the transport interface is capable of direct communication via the microprocessor interface with a microprocessor located on the motherboard.

8. The accelerator module according to claim 7 , wherein the bitstream is capable of being instantiated in the first programmable logic device using the programmable logic thereof to additionally provide an arbitration block for communication with the second memory via the transport interface.

9. The accelerator module according to claim 8 , further comprising:

third memory coupled to the circuit board;

the bitstream capable of being instantiated in the first programmable logic device using the programmable logic thereof to additionally provide a memory interface for communication with the third memory;

the transport interface capable of being used to communicate data between the microprocessor interface and the third memory via the transport interface as arbitrated by the arbitration block.

10. The accelerator module according to claim 9 , wherein:

the transport interface is capable of being used to communicate data to a user design instantiated in the programmable logic of the first programmable logic device;

the controller is a second programmable logic device; and

the arbitration block is configured to support Direct Memory Access.

11. The accelerator module according to claim 6 , further comprising:

a second memory and a third memory coupled to the circuit board; and

the bitstream capable of being instantiated in the first programmable logic device using the programmable logic thereof to additionally provide a first memory interface and a second memory interface for communication with the second memory and the third memory, respectively.

12. The accelerator module according to claim 11 , wherein:

the second memory is Static Random Access Memory (“SRAM”);

the second memory interface is an SRAM interface;

the third memory is Dynamic Random Access Memory (“DRAM”); and

the third memory interface is a DRAM interface.

13. The accelerator module according to claim 11 , wherein:

the second memory is Reduced Latency Dynamic Random Access Memory (“RLDRAM”);

the second memory interface is an RLDRAM interface;

the third memory is Dynamic Random Access Memory (“DRAM”); and

the third memory interface is a DRAM interface.

14. The accelerator module according to claim 6 , further comprising:

a first bus coupled between the controller and the first programmable logic device for communication therebetween;

the controller being a second programmable logic device;

a second bus coupled between the controller and the first programmable logic device; and

the second bus dedicated for passing configuration information from the second programmable logic device to the first programmable logic device for instantiation of the bitstream in the programmable logic of the first programmable logic device.

15. The accelerator module according to claim 14 , further comprising:

a second memory coupled in parallel with the first memory; and

the second memory being a Random Access Memory.

16. The accelerator module according to claim 15 , wherein:

the first memory is flash memory;

the second memory is a either a Reduced Latency Dynamic Random Access Memory or a Static Random Access Memory;

the first programmable logic device is a Field Programmable Gate Array; and

the second programmable logic device is a Complex Programmable Logic Device.

17. The accelerator module according to claim 6 , wherein the transport interface includes transport links.

18. The accelerator module according to claim 17 , wherein:

banks, including portions thereof, of the first programmable logic device are assigned to the transport links; and

the transport links are segregated among the banks to be mutually exclusive such that no two or more of the transport links has any common bank of the banks.

19. A method for accelerating data processing, comprising:

initiating a boot sequence for an accelerator module directly coupled to a microprocessor interface;

configuring a first programmable logic device of the accelerator module responsive to a bitstream to instantiate a first interface in the first programmable logic device;

obtaining a configuration bitstream via the first interface instantiated in the first programmable logic device;

the first interface capable of direct communication with a microprocessor coupled to the microprocessor interface;

instantiating a user design in the first programmable logic device responsive to the configuration bitstream; and

co-processing an algorithm or portion thereof using the user design.

20. The method according to claim 19 , further comprising:

storing the configuration bitstream obtained in memory of the accelerator module.

21. The method according to claim 20 , further comprising:

instantiating a second interface in the first programmable logic device responsive to the bitstream; and

communicating the configuration bitstream via the first interface to the first programmable logic device and then to the memory via the second interface.

22. The method according to claim 20 , further comprising:

sending a command and an address from the microprocessor to the first programmable logic device via the first interface;

the address indicating a location in the memory for accessing the configuration bitstream; and

the command indicating a type of configuration to perform at least for the instantiating of the user design.

23. The method according to claim 22 , wherein the type of configuration to perform includes a full reconfiguration or a full initial configuration of the user design in the first programmable logic device.

24. The method according to claim 22 , wherein the type of configuration to perform includes a partial reconfiguration of the user design in the first programmable logic device.

25. The method according to claim 22 , wherein the configuration bitstream is obtained in part by translating a high-level computer language description of the user design into a Hardware Description Language version thereof.

26. The method according to claim 22 , wherein the high-level computer language description makes parallelism visible to the user.

27. The method according to claim 21 , wherein the configuration bitstream is obtained in part using a fixed placement for the second interface.