MEMS based RF components with vertical motion and parallel-plate structure and manufacture thereof using standard CMOS technologies

1. A process of manufacturing microstructures, said process comprising constructing microstructures in a chip with at least one vertically movable component using a CMOS process, achieving vertical motion by constructing an air gap beneath the at least one vertically movable component, creating the air gap by selectively removing one or more sacrificial layers using a CMOS process, one or more of the sacrificial layers including at least one metal layer.

2. A process as claimed in claim 1 , including the steps of constructing parallel plate microstructures, being parallel plates comprising a top plate and a bottom plate, constructing said top plate to be inside at least one vertically movable component and locating said air gap between said top plate and said bottom plate, said top plate and said bottom plate being constructed of at least two composite structural layers.

3. A process as claimed in claim 2 , including the step of constructing each composite structural layer comprises at least one metal layer and at least one dielectric layer.

4. A process as claimed in claim 1 , including the steps of integrating said at least one vertically movable component in said chip with active CMOS circuitry.

5. A process as claimed in claim 4 , wherein said chip has a substrate and said process includes the steps of forming a deep trench in said substrate to improve performance of said at least one vertically movable component.

6. A process as claimed in claim 1 , including the steps of constructing said microstructures using said CMOS process comprised of dry reactive-ion etching and wet etching processes.

7. A process as claimed in claim 6 , including the steps of using anisotropic reactive-ion etching of a CMOS dielectric layer and using one of multiple metal layers of a CMOS layer stack as an etch resistant mask with portions of the CMOS dielectric layer which are not covered by said mask being removed to expose a sacrificial layer and a CMOS substrate.

8. A process as claimed in claim 7 , including the steps of using wet isotropic and anisotropic etching of the exposed sacrificial layer and the CMOS substrate for a controlled amount of time, respectively.

9. A process as claimed in claim 8 wherever the microstructures are MEMS structures, including the step of removing the metal sacrificial layer to form an air gap between plates of the MEMS structures.

10. A process as claimed in claim 9 , including the steps of removing the CMOS substrate and forming a trench under the MEMS structure to improve an RF performance and removing said etch resistant mask.

11. A process as claimed in claim 10 wherein the plates are parallel plates, including the step of drying the MEMS structures in a critical-point dryer system in order to prevent stiction between the parallel plates.

12. A process as claimed in claim 11 , including the steps of carrying out a second reactive-ion etching of the CMOS dielectric layer for a controlled amount of time to remove portions of the dielectric layer on top of a top plate of the MEMS structure and also on top of bonding pads for electrical contact and signal routing.

13. A process as claimed in claim 9 , including the step of thinning the dielectric layer present in a metal/dielectric layer and dielectric/metal/dielectric composite layers of top and bottom plates of the microstructure, respectively, by controlled wet etching.

14. A process as claimed in claim 7 , including the steps of carrying out controlled anistropic and then isotropic reactive-ion etching of the CMOS substrate right after a first reactive-ion etching of the CMOS dielectric layer and before the wet etching of the sacrificial layer and of the CMOS substrate.

15. A process as claimed in claim 6 , including the steps of using the process to produce one or more of a MEMS variable capacitor, an integrated tunable band pass filter and RF-MEMS tunable matching networks.

16. A process as claimed in claim 1 , including the steps of forming multiple interconnect metal layers separated by a dielectric layer.

17. A process as claimed in claim 1 including the step of fabricating one or more microstructures selected from the group of a MEMS variable capacitor; an integrated tunable bandpass filter; RF tunable matching networks, a tunable matching circuit having a lump element network; a tunable matching circuit where there is a controller; RF tunable matching networks with a coplanar waveguide transmission line periodically loaded with parallel-plate capacitive MEMS bridges between signal and ground lines, a controller to change a state of each of the MEMS bridges; CMOS reconfigurable amplifiers; a shunt type capacitive RF-MEMS switch having a coplanar waveguide transmission line and a vertically movable component; a series type capacitive RF-MEMS switch having a coplanar waveguide transmission line with a gap along a signal line; and a parallel-plate microstructure with vertical motion located in one of a phase shifter, voltage-controlled oscillator, switch matrices and any other reconfigurable system built using CMOS technology.