Method for manufacturing semiconductor device capable of increasing current drivability of PMOS transistor
A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate.
1. A method for manufacturing a semiconductor device, comprising the step of forming an isolation layer having a structure in which an insulation layer is filled in trenches defined in a semiconductor substrate having a PMOS region;
the step of forming the isolation layer comprising;
forming a buffer layer selectively on sidewalls of the trenches, wherein the buffer layer is formed as a layer made of any one of Ge, Al, Zr, Hf and B, or an oxide layer in which at least one of Si, Ge, Al, Zr, Hf, and B is oxidized to an oxygen lacking state; and
oxidizing the buffer layer such that a distance between silicon lattices in the semiconductor substrate is decreased due to an increase in volume of the oxidized buffer layer, such that compressive stress is applied in a channel length direction of the PMOS region.
2. The method according to claim 1 , wherein oxidation of the buffer layer is conducted at a temperature of about 700 to 1,000° C. and at a pressure of about 200 to 760 Torr.
3. A method for manufacturing a semiconductor device, comprising the steps of:
defining trenches in a semiconductor substrate having a PMOS region;
forming a buffer layer selectively on sidewalls of the trenches, wherein the buffer layer is formed as a layer made of any one of Ge, Al, Zr, Hf and B, or an oxide layer in which at least one of Si, Ge, Al, Zr, Hf, and B is oxidized to an oxygen lacking state;
forming an insulation layer to fill the trenches having the buffer layer formed on the sidewalls thereof;
annealing the semiconductor substrate such that the buffer layer is oxidized and a distance between silicon lattices in the semiconductor substrate is decreased due to an increase in the volume of the oxidized buffer layer, such that compressive stress is applied in a channel length direction of a PMOS transistor;
removing portions of the insulation layer and thereby forming an isolation layer; and
forming the PMOS transistor on the PMOS region of the semiconductor substrate.
4. The method according to claim 3 , wherein, after the step of defining the trenches and before the step of forming the buffer layer, the method further comprises the steps of:
forming a sidewall oxide on surfaces of the trenches; and
forming a liner nitride layer on the semiconductor substrate including the sidewall oxide.
5. The method according to claim 4 , wherein, after the step of forming the liner nitride layer, the method further comprises the step of:
forming a liner oxide layer on the liner nitride layer.
6. The method according to claim 3 , wherein the step of forming the buffer layer selectively on the sidewalls of the trenches comprises the steps of:
depositing a buffer layer on the semiconductor substrate including the surfaces of the trenches; and
etching the buffer layer such that the buffer layer remains only on sidewalls of the trenches.
7. The method according to claim 3 , wherein the insulation layer comprises an oxide layer formed through at least one selected from group consisting of a high density plasma (HDP) process and a spin-on dielectric (SOD) process.
8. The method according to claim 3 , wherein annealing is conducted at a temperature of about 700 to 1,000° C. and at a pressure of about 200 to 760 Torr.