Image sensor package and forming method of the same
View Patent ↗An image sensor package comprises a substrate, a chip mounted over the substrate. A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the micro lens. A redistributed conductive layer is formed over the molding material to connect to a pad of the chip. Metal pads are formed on via structure as connecting points with PCB. A cover layer is formed over the substrate to isolate the metal pads.
1. A method of making an image sensor package, comprising:
providing a chip with a protection layer formed on a micro lens;
filling a molding material surrounding said chip;
providing a substrate mounting on said chip;
forming a first dielectric layer over said molding material and said chip, said first dielectric layer having a first opening and a second opening exposing a micro lens area formed therein;
removing part of said first dielectric layer and said molding material to form a third opening;
forming a redistributed conductive layer over said first dielectric layer to fill into said first opening to connect pad of said chip;
forming a via structure to fill into said third opening;
forming a second dielectric layer over said first dielectric layer and said redistributed conductive layer, said second dielectric layer having a fourth opening exposing said micro lens area;
forming metal pads on said via structure;
forming a cover layer over said substrate.
2. The method claim 1 , wherein said first opening and said second opening is formed by employing a lithography process and an etching process.
3. The method claim 1 , wherein said third opening is formed by employing a lithography process and an etching process.
4. The method claim 1 , wherein said third opening is formed by employing a laser drilling process.
5. The method claim 1 , wherein said redistributed conductive layer is formed by employing an electro-plating process.
6. The method claim 1 , wherein said via structure is formed by employing an electro-plating process.
7. The method claim 1 , wherein said fourth opening is formed by employing a lithography process and an etching process.
8. The method claim 1 , further comprising a step of performing a half etching process of said substrate.