High breakdown voltage double-gate semiconductor device
A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.
1. A device comprising:
a substrate;
a source region defined within the substrate;
a first gate including
a dielectric layer disposed on the substrate and over a channel region defined within the substrate adjoining the source region, and
an electrically conductive gate layer disposed on the dielectric layer;
a well region defined within the substrate and including
a drain region defined within the well region, and
a second gate defined within the well region between the drain region and the first gate; and
an electrically conductive path between the channel region and the well region, the electrically conductive path comprising a first doped region within the well, a second doped region outside of the well and adjoining the channel, and an electrically conductive layer disposed on the substrate and in contact with both of the first and second doped regions.
2. The device of claim 1 further comprising control circuitry coupled between the first gate and the second gate and configured to bias the second gate as a function of a bias applied to the first gate.
3. The device of claim 1 wherein the substrate comprises P doping, the source and drain regions both comprise N doping, the well comprises N doping, and the second gate comprises P doping.
4. The device of claim 2 wherein the control circuitry comprises a capacitor.
5. The device of claim 1 wherein the electrically conductive layer comprises polysilicon.
6. The device of claim 1 wherein the electrically conductive layer comprises a metal.