Efficient transistor structure
An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first shape that surrounds the second drain region. A connecting gate region connects the first and second gate regions. A first source region is arranged adjacent to and on one side of the first gate region, the second gate region and the connecting gate region. A second source region is arranged adjacent to and on one side of side of the first gate region, the second gate region and the connecting gate region.
1. An integrated circuit, comprising:
a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines;
a first gate region having a first shape surrounding said first drain region;
a second drain region having said symmetric shape;
a second gate region having said first shape surrounding said second drain region;
a connecting gate region connecting said first and second gate regions;
a first source region arranged adjacent to and on one side of said first gate region, said second gate region and said connecting gate region;
a second source region arranged adjacent to and on another side of said first gate region, said second gate region and said connecting gate region opposite said one side; and
first and second substrate contacts arranged in said first and second source regions, respectively.
2. The integrated circuit of claim 1 , wherein said symmetric shape tapers as a distance from a center of said symmetric shape increases.
3. The integrated circuit of claim 1 , wherein said integrated circuit includes laterally-diffused MOSFET transistors.
4. The integrated circuit of claim 1 , wherein said symmetric shape is a circular shape.
5. The integrated circuit of claim 1 , wherein said symmetric shape is an elliptical shape.
6. The integrated circuit of claim 1 , wherein said symmetric shape is a polygonal shape.
7. The integrated circuit of claim 1 , wherein said symmetric shape is a hexagonal shape.
8. The integrated circuit of claim 1 , wherein the first and second substrate contacts are aligned with the connecting gate region in a first direction.
9. The integrated circuit of claim 1 , further comprising third and fourth substrate contacts arranged in the first and second drain regions, respectively.
10. An integrated circuit, comprising:
a first drain region including a first substrate contact;
a first gate region surrounding the first drain region;
a second drain region including a second substrate contact;
a second gate region surrounding the second drain region;
a connecting gate region connecting the first and second gate regions;
a first source region arranged adjacent to and on a first side of the first gate region, the second gate region and the connecting gate region, the first source region including a third substrate contact; and
a second source region arranged adjacent to and on a second side of the first gate region, the second gate region and the connecting gate region, the second side including a fourth substrate contact and being opposite the first side.
11. The integrated circuit of claim 10 , wherein the first and second drain regions surround the first and second substrate contacts, respectively.
12. The integrated circuit of claim 10 , wherein the first and second source regions surround the third and fourth substrate contacts, respectively.
13. The integrated circuit of claim 10 , wherein the first, second, third, and fourth substrate contacts have one of a rectangle, circle, cross, and diamond shape.
14. The integrated circuit of claim 10 , wherein an area of the first substrate contact is greater than 2 nm, wherein n is a total number of substrate contacts located in the first source region, and wherein m is an area of one of the substrate contacts located in the first source region.
15. The integrated circuit of claim 10 , wherein the third and fourth substrate contacts are aligned with the connecting gate region in a first direction.